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US 11,106,600 B2Granted
Cache replacement based on translation lookaside buffer evictions
AssigneeAdvanced Micro Devices, Inc.
InventorsGabriel H. Loh, Paul Moyer
Life of this patent
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Abstract
A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.
Claims20
A method comprising:
- communicating, at a translation lookaside buffer (TLB) of a processor, a memory page address corresponding to a TLB entry to a cache logic of a cache in response to the TLB entry being evicted from the TLB;
- measuring a performance characteristic of the processor;
- and
- invalidating one or more cache lines of the cache corresponding to the memory page address or reducing a retention priority of the one or more cache lines based on the measured performance characteristic.
1 more element
A method, comprising:
- in response to eviction of a translation lookaside buffer (TLB) entry indicating a virtual-to-physical address translation from a TLB of a processor, adjusting, for a cache, a cache replacement priority of cache lines storing data or instructions having addresses corresponding to a physical address or a virtual address of the TLB entry wherein adjusting the cache replacement priority maintains one or more of the cache lines in a valid state.
A processor, comprising:
- a translation lookaside buffer (TLB);
- a cache;
- and
- cache logic configured to adjust a cache replacement priority of one or more cache lines of the cache storing data or instructions having an address corresponding to a physical or virtual address of an entry of the TLB in response to receiving a communication from the TLB that the entry of the TLB has been evicted, wherein adjusting the cache replacement piority maintains at least one of the cache lines in a valid state.
1 more element
Dependencies are inferred from the claim text.