Time-interleaved successive approximation register analog to digital converter with grouped digital to analog capacitors

A method of increasing power efficiency and speed of a digital-to-analog converter (DAC), said method comprising:

• providing a top plate having a comb-like structure with a plurality of metallic fingers, the top plate fingers having a uniform length, and all being electrically coupled together to form an output, wherein each of the top plate fingers is of a uniform length;
• providing a plurality of bottom plates forming bottom plate bit fingers, wherein each of the bottom plate bit fingers is interleaved between two adjacent top plate fingers;
• disposing an insulator between the top plate fingers and each of the plurality of bottom plates to thereby create capacitance between the top plate and the plurality of bottom plates bit fingers;
• providing a plurality of dummy fingers that are interleaved between some of the bit fingers to thereby provide shielding between bit fingers;
• wherein the plurality of bottom plate bit fingers are inputs that represent bits, wherein the bits are formed by powers of two such that the first bit has a single bit finger, the second bit has two bit fingers, the third bit has four bit fingers, and so on until all of the bits are represented by the appropriate number of bit fingers;
• and
• increasing power efficiency by grouping the bit fingers for each bit so as to be adjacent to each other in bit finger groups to thereby having less exposure to parasitic capacitances, and wherein each of the bottom plate bit fingers may be full length or half-length to thereby achieve a desired capacitive scaling.