Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by limit cycle oscillation (LCO) and other factors

A digital low-dropout voltage regulator (DLDO) having a configuration that mitigates performance degradation of the DLDO caused by limit cycle oscillation (LCO), the DLDO comprising:

• a clocked comparator circuit having at least first and second input terminals, an output terminal and a clock terminal, the first terminal receiving a reference voltage Vref, the second input terminal receiving an output voltage signal Vout output from an output voltage terminal of the DLDO, the clock terminal receiving a DLDO clock signal, clk, having a preselected pulse width, the comparator comparing the reference voltage signal with the output voltage signal and outputting a comparator output voltage, Vcmp;
• an array of N power transistors electrically connected in parallel with one another, where N is a positive integer that is greater than or equal to one, each power transistor having first, second and third terminals, the first terminal of each power transistor being electrically coupled to the output voltage terminal of the DLDO;
• a digital controller comprising control logic configured to activate and deactivate the power transistors of the DLDO in accordance with a preselected activation/deactivation control scheme, the digital controller having an input terminal, a clock terminal and a plurality of output terminals, the clock terminal of the digital controller receiving the DLDO clock signal, clk, the second terminal of each power transistor being electrically coupled to one of the output terminals of the digital controller for receiving a respective control signal from the digital controller, the control signals causing the power transistors to be turned ON or OFF in accordance with the preselected activation/deactivation control scheme;
• and
• a clock pulsewidth reduction circuit configured to receive an input clock signal, CLK, having a first pulsewidth and to generate the DLDO clock signal, clk, having the preselected pulsewidth, the preselected pulsewidth of the DLDO clock signal, clk, being smaller than the first pulsewidth of the input clock signal, CLK, an output terminal of the clock pulsewidth reduction circuit being electrically coupled to the clock terminals of the clocked comparator and the digital controller for delivering the DLDO clock signal, clk, to the clocked comparator and to the digital controller.