Integrated circuit including multi-height standard cell and method of designing the same

An integrated circuit comprising:

• a semiconductor substrate;
• a first power rail, a second power rail, and a third power rail formed above the semiconductor substrate, extending in a first direction and arranged sequentially in a second direction perpendicular to the first direction;
• a first flip-flop formed in a first region between the first power rail and the second power rail, and comprising a first master latch and a first slave latch;
• a second flip-flop formed in a second region between the second power rail and the third power rail, and comprising a second master latch and a second slave latch;
• and
• a first clock gate line, a second clock gate line, a third clock gate line, and a fourth clock gate line formed above the semiconductor substrate, extending in the second direction to pass through the first region and the second region,
• wherein the first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction, and
• wherein the first clock gate line and the second clock gate line provide a clock signal and an inverted clock signal to the first master latch and the second master latch, and the third clock gate line and the fourth clock gate line provide the clock signal and the inverted clock signal to the first slave latch and the second slave latch.

A method of designing an integrated circuit, the method comprising:

• receiving input data defining an integrated circuit;
• providing, in a standard cell library, at least one multi-height standard cell;
• performing placement and routing based on the input data and the standard cell library;
• and
• generating output data defining the integrated circuit based on a result of the placement and the routing,
• wherein the multi-height standard cell comprises:
• a semiconductor substrate;
• a first power rail, a second power rail, and a third power rail formed above the semiconductor substrate, extending in a first direction and arranged sequentially in a second direction perpendicular to the first direction;
• and
• a first clock gate line, a second clock gate line, a third clock gate line, and a fourth clock gate line formed above the semiconductor substrate, extending in the second direction to pass through a first region between the first power rail and the second power rail, and a second region between the second power rail and the third power rail,
• wherein the first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction.