Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers

A method for constructing a package structure comprising:

• forming a first stack of redistribution layers on a surface of a carrier substrate;
• forming a trench in the first stack of redistribution layers;
• mounting a chip interconnect bridge within the trench using a die attach film;
• forming a second stack of redistribution layers over the first stack of redistribution layers and a top side of the chip interconnect bridge, wherein the first and second stacks of redistribution layers form a first fan-out redistribution layer structure;
• direct chip attaching at least a first integrated circuit chip and a second integrated circuit chip to an upper surface of the second stack of redistribution layers, wherein the second stack of redistribution layers comprises input/output connections between contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips;
• removing the carrier substrate to expose a bottom side of the first fan-out redistribution layer structure and a bottom side of the die attach film;
• and
• forming a second fan-out redistribution layer structure on the exposed bottom sides of the first fan-out redistribution layer structure and the die attach film, wherein the second fan-out redistribution layer structure comprises vertical contacts formed through the die attach film in contact with a bottom side of the chip interconnect bridge.

A method for constructing a package structure comprising:

• forming a first stack of redistribution layers on a surface of a carrier substrate;
• forming a trench in the first stack of redistribution layers;
• mounting a chip interconnect bridge within the trench;
• forming a second stack of redistribution layers over the first stack of redistribution layers and a top side of the chip interconnect bridge, wherein the first and second stacks of redistribution layers form a first fan-out redistribution layer structure;
• direct chip attaching at least a first integrated circuit chip and a second integrated circuit chip to an upper surface of the second stack of redistribution layers, wherein the second stack of redistribution layers comprises input/output connections between contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips;
• and
• removing the carrier substrate to expose a bottom side of the first fan-out redistribution layer structure;
• wherein forming the trench in the first stack of redistribution layers comprises:
• etching a trench through at least one redistribution layer of the first stack of redistribution layers down to a surface of an underlying redistribution layer;
• and
• bonding the chip interconnect bridge to the surface of the underlying redistribution layer exposed at a bottom of the trench using solder bumps.