# US 11,093,213 B1 · Cryptographic computer machines with novel switching devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,093,213 B1 - Document ID: US11093213B1 - Status: Granted - Kind: B1 - Application number: 16/172,584 - Filed: 2018-10-26 - Granted: 2021-08-17 - Earliest claimed: 2010-12-29 - Assignees: Ternarylogic LLC - Applicants: Peter Lablans - Inventors: Peter Lablans - Web page: https://patentgrep.com/patent/US11093213B1 ## CPC - G06F 7/4876: {Multiplying} - G06F 7/724: {Finite field arithmetic (for error detection or correction in general H03M13/00, in computers G06F11/10)} - G06F 5/012: {in floating-point computations} - H03M 7/00: Conversion of a code where information is represented by a given sequence or number of digits to a code where the same {, similar or subset of} information is represented by a different sequence or number of digits - H03M 13/15: Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence) - H03M 13/158: {Finite field arithmetic processing} - H04L 9/06: the encryption apparatus using shift registers or memories for block-wise {or stream} coding, e.g. DES systems {or RC4; Hash functions; Pseudorandom sequence generators} - H04L 9/0631: {Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms} - H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC} - H04L 9/065: {Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3} - H04L 9/0844: {with user authentication or key authentication, e.g. ElGamal, MTI, MQV-Menezes-Qu-Vanstone protocol or Diffie-Hellman protocols using implicitly-certified keys} - H04L 9/3066: {involving algebraic varieties, e.g. elliptic or hyper-elliptic curves} - H04L 9/3093: {involving Lattices or polynomial equations, e.g. NTRU scheme} - H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit - H03M 13/1515: {Reed-Solomon codes} - H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes - H03M 13/23: using convolutional codes, e.g. unit memory codes - H04L 2209/34: Encoding or coding, e.g. Huffman coding or error correction - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Operational n-state digital gates execute Finite Lab-transformed (FLT) n-state switching functions or n-state switching function tables to process n-state signals provided on at least 2 inputs to generate an n-state signal on an output, with n>2, n>3 and n>64. The FLT is an enhancement of a computer architecture. Cryptographic apparatus and methods apply circuits that are characterized by FLT-ed addition and multiplication over finite field GF(n) or by addition and multiplication modulo-n that are modified in accordance with reversible n-state inverters, and are no longer characterized by known operations. Known cryptographic methods executed with novel n-state digital gates include encryption/decryption, public key generation, message digest and Elliptic Curve Cryptography wherein one n-state switching function is replaced by an FLT'ed n-state switching function. ## Claims ### Claim 1 A cryptographic computer system, comprising: a first and a second computer, each having a processor and each processor configured to execute instructions to perform a modified n-state operation, the modified n-state operation being characterized by an n-state operation that is modified by a first n-state reversible inverter applied to n-state data being inputted on two inputs of the n-state operation and a second n-state reversible inverter being applied to n-state data being outputted by an output of the n-state operation, with n an integer greater than 2 and an n-state being one of n states, wherein: the n-state operation characterizes an n-state switching function operating on n-state data elements to generate n-state data elements, the n-state operation being selected from the group consisting of modulo-n addition, modulo-n multiplication, known addition over a Finite Field (GF(n)), and known multiplication over GF(n) and the modified n-state operation is not selected from the group consisting of modulo-n addition, modulo-n multiplication, known addition over GF(n) and known multiplication over GF(n); the first computer and second computer enabled to exchange n-state data generated by a cryptographic operation selected from the group consisting of encryption, public key cryptography, signature generation, message digest generation, and elliptic curve cryptography wherein the modified n-state operation is applied. ### Claim 2 (depends on 1) The cryptographic computer system of claim 1, wherein the cryptographic operation is performed in accordance with an Advanced Encryption Standard (AES) wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 3 (depends on 1) The cryptographic computer system of claim 1, wherein the cryptographic operation is a public key exchange operation in accordance with Diffie-Hellman key exchange wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 4 (depends on 1) The cryptographic computer system of claim 1, wherein the cryptographic operation is a public key exchange operation in accordance with Rivest-Shamir-Adleman (RSA) cryptography wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 5 (depends on 1) The cryptographic computer system of claim 1, wherein the cryptographic operation is a public key exchange operation in accordance with Learning-with-Errors (LWE) cryptography wherein at least one n-state operation is replaced by modified n-state operation. ### Claim 6 (depends on 1) The cryptographic computer system of claim 1, wherein the cryptographic operation is a message digest generation. ### Claim 7 (depends on 1) The cryptographic computer system of claim 1, wherein the message digest generation is selected from the group consisting of Secure Hash Algorithm (SHA) family of standards wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 8 (depends on 1) The cryptographic computer system of claim 1, wherein the modified n-state operation is characterized by n-state inverter modification of the addition modulo-n or addition over GF(n) and the modified n-state operation has a zero-element that is not 0. ### Claim 9 (depends on 1) The cryptographic computer system of claim 1, wherein the modified n-state operation is characterized by n-state inverter modification of the multiplication modulo-n or multiplication over GF(n) and the modified n-state operation has a zero-element that is not 0. ### Claim 10 (depends on 1) The cryptographic computer system of claim 1, wherein a combination of the first and second reversible inverters establishes identity. ### Claim 11 A cryptographic method, comprising: performing by a first computer of a modified n-state operation characterized by an n-state operation wherein input n-state data provided on two inputs of the n-state operation is modified by a first n-state reversible inverter and n-state data being generated by the n-state operation is modified by a second n-state reversible inverter with n being an integer greater than 2, wherein the n-state operation is selected from the group consisting of modulo-n addition, modulo-n multiplication, known addition over a Finite Field GF(n) and known multiplication over a Finite Field GF(n) and the modified n-state operation is not selected from the group consisting of modulo-n addition, modulo-n multiplication, known addition over GF(n) and known multiplication over GF(n); generating by the first computer of data in a cryptographic operation selected from the group consisting of encryption, public key cryptography, message digest generation, and elliptic curve cryptography wherein the modified n-state operation is used; and exchanging data generated in the cryptographic operation by the first computer with a second computer. ### Claim 12 (depends on 11) The cryptographic method of claim 11, wherein the cryptographic operation is a public key exchange operation in accordance with Diffie-Hellman key exchange wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 13 (depends on 11) The cryptographic method of claim 11, wherein the cryptographic operation is a public key exchange operation in accordance with Rivest-Shamir-Adleman (RSA) cryptography wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 14 (depends on 11) The cryptographic method of claim 11, wherein the cryptographic operation is a public key exchange operation in accordance with Learning-with-Errors (LWE) cryptography wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 15 (depends on 11) The cryptographic method of claim 11, wherein the cryptographic operation is message digest generation selected from the group consisting of Secure Hash Algorithm (SHA) family of standards wherein at least one n-state operation is replaced by the modified n-state operation. ### Claim 16 (depends on 11) The cryptographic method of claim 11, wherein the modified n-state operation is characterized by modification of the multiplication modulo-n or multiplication over GF(n) and the modified n-state operation has a zero-element that is not 0. ### Claim 17 (depends on 11) The cryptographic method of claim 11, wherein a combination of the first and second reversible inverters establishes identity. ### Claim 18 A cryptographic computer device, comprising: a processor connected to a memory, the processor enabled to execute instructions retrieved from the memory; the processor being configured to perform the steps of a modified n-state operation which is characterized by a modification of an n-state operation the modification including a first n-state reversible inverter applied to n-state data being inputted to the n-state operation and a second n-state reversible inverter being applied to n-state data being outputted by the n-state operation with n being greater than 2, wherein: the n-state operation being selected from the group consisting of modulo-n addition, modulo-n multiplication, known addition over a Finite Field (GF(n)) and known multiplication over GF(n) and the modified n-state operation is not selected from the group consisting of modulo-n addition, modulo-n multiplication, known addition over GF(n) and known multiplication over GF(n); communication circuitry to transmit n-state data generated by the n-state processing circuit in a cryptographic operation selected from the group consisting of encryption, public key cryptography, message digest generation, and elliptic curve cryptography wherein the modified n-state operation is applied. ### Claim 19 (depends on 18) The cryptographic computer device of claim 18, wherein a combination of the second reversible n-state inverter and the first reversible n-state inverter establishes identity.