Secure system on chip
AssigneeIndustry-University Cooperation Foundation Hanyang University
InventorsDong Kyue Kim, Ji-Hoon Kim
Life of this patent
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Abstract
Disclosed is a secure semiconductor chip. The semiconductor chip is, for example, a system-on-chip. The system-on-chip is operated by connecting normal IPs to a processor core included therein via a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is separately provided. Security IPs for performing a security function or handling security data are connected to the secure bus. The secure semiconductor chip can perform required authentication while shifting between a normal mode and a secure mode.
Claims16
A semiconductor chip comprising:
- a processor core;
- a first group comprising elements connected to the processor core by a first bus;
- and
- a second group comprising elements connected to the processor core by a second bus and configured to operate in a secure mode,
- wherein the second group processes data by using a memory address different from that of the first group, and
- wherein the processor core partitions a memory area into a code area and a data area and comprises a memory protection unit, the memory protection unit configured to prohibit writing in the code area and prohibit execution in the data area,
- wherein the processor core comprises a RISC (reduced instruction set computing)-V processor, the RISC-V processor being a 32-bit RISC type embedded processor,
- wherein the second bus comprises a hidden bus implemented by using an ASR (application specific register) of the RISC-V processor as an address space for controlling elements included in the second group.
An operation method for a semiconductor system-on-chip, the operation method comprising:
- performing mutual authentication with an outside trusted authority, the mutual authentication performed by an authentication part;
- and
- activating a first group comprising elements connected to the processor core by a first bus and deactivating elements connected to the processor core by a second bus and configured to operate in a secure mode, if the authentication is not successful,
- wherein the second group processes data by using a memory address different from that of the first group, and
- wherein the processor core partitions a memory area into a code area and a data area and comprises a memory protection unit, the memory protection unit configured to prohibit writing in the code area and prohibit execution in the data area,
- wherein the processor core comprises a RISC (reduced instruction set computing)-V processor, the RISC-V processor being a 32-bit RISC type embedded processor, and
- wherein the second bus comprises a hidden bus implemented by using an ASR (application specific register) of the RISC-V processor as an address space for controlling elements included in the second group.
Dependencies are inferred from the claim text.