Rapid sensing value estimation circuit and method thereof

A rapid sensing value estimation circuit, comprising:

• a first sensing unit configured to perform sensing to generate a first sensing signal;
• an integral sensing circuit electrically connected to the first sensing unit and including:
• an operational amplifier having a first input terminal electrically connected to the first sensing unit and connected to an output terminal of the operational amplifier through an integrating capacitor, and having a second input terminal being grounded, wherein the output terminal of the operational amplifier is an integration node, and the operational amplifier receives the first sensing signal and generates an integration voltage at the integrating node;
• a comparator having a first input terminal electrically connected to the integration node, and a second input terminal electrically connected to a first reference voltage, wherein in response to the integration voltage exceeding the first reference voltage, the comparator is configured to generate a trigger reset signal at the output terminal of the comparator, wherein the trigger reset signal is used to reset the integration voltage;
• and
• a first counter configured to count the trigger reset signal within an integration time to generate and correspondingly output a first count value, wherein the first counter has a first maximum count value within the integration time;
• and
• a rapid estimation circuit including:
• a clock generator configured to generate a clock signal having a first frequency;
• a second counter electrically connected to the clock generator and configured to count the clock signal within the integration time to generate and correspondingly output a second count value, wherein the second counter has a second maximum count value related to the first frequency within the integration time, and the second maximum count value is greater than the first maximum count value;
• a first digital comparator configured to determine whether the second count value exceeds a first predetermined count value when the first count value increases;
• and
• an arithmetic module configured to, in response to the first digital comparator determining that the second count value exceeds the first predetermined count value, estimate the first count value at an end of the integration time according to a ratio of the second maximum count value to the second count value and the first count value when the second count value exceeding the first predetermined count value, to generate an estimated count value result.