Enclosure-to-board interface with tamper-detect circuit(s)

A tamper-respondent assembly comprising:

• a circuit board with a main surface, the main surface being an upper main surface of the circuit board;
• at least one electronic component to be protected, the at least one electronic component being mounted on the main surface of the circuit board;
• an enclosure with an enclosure edge mounted to the main surface of the circuit board along an enclosure-to-board interface region of the main surface of the circuit board, the enclosure facilitating enclosing the at least one electronic component mounted on the main surface of the circuit board within a secure volume;
• a tamper-respondent electronic circuit structure facilitating defining the secure volume, the tamper-respondent electronic circuit structure comprising one or more tamper-detect circuits comprising at least one conductive trace on the main surface of the circuit board within the enclosure-to-board interface region underneath the enclosure edge mounted to the main surface of the circuit board, the at least one conductive trace comprising stress rise regions within the enclosure-to-board interface region on the main surface of the circuit board underneath the enclosure edge mounted to the main surface of the circuit board to facilitate detecting a tamper event at the enclosure-to-board interface between the enclosure and the circuit board, the stress rise regions being discrete stress concentration points in the at least one conductive trace;
• and
• an adhesive securing the enclosure to the circuit board, the adhesive contacting, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface region underneath the enclosure edge mounted to the main surface of the circuit board, including at the stress rise regions of the at least one conductive trace.

A fabrication method comprising:

• fabricating a tamper-respondent assembly, the fabricating comprising:
• providing a circuit board with a main surface on which at least one electronic component is mounted;
• providing an enclosure with an enclosure edge mounted to the main surface the circuit board along an enclosure-to-board interface region on the main surface of the circuit board, the enclosure facilitating enclosing the at least one electronic component mounted on the main surface of the circuit board within a secure volume;
• providing a tamper-respondent electronic circuit structure facilitating defining the secure volume, the tamper-respondent electronic circuit structure comprising one or more tamper-detect circuits comprising at least one conductive trace on the main surface of the circuit board within the enclosure-to-board interface region underneath the enclosure edge mounted to the main surface of the circuit board, the at least one conductive trace comprising stress rise regions within the enclosure-to-board interface region on the main surface of the circuit board underneath the enclosure edge mounted to the main surface of the circuit board to facilitate detecting a tamper event at the enclosure-to-board interface between the enclosure and the circuit board, the stress rise regions being discrete stress concentration points in the at least one conductive trace;
• and
• securing the enclosure to the circuit board using an adhesive, the adhesive contacting, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface region underneath the enclosure edge mounted to the main surface of the circuit board, including at the stress rise regions of the at least one conductive trace.