Back to results
US 11,082,544 B2Granted
Compact timestamp, encoders and decoders that implement the same, and related devices, systems and methods
AssigneeMicrochip Technology Incorporated
InventorJason Sachs
Life of this patent
Estimating the term…
Abstract
Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.
Claims37
An encoder, comprising:
- one or more linear feedback shift registers (LFSRs) configured to store N bits of LFSR state information for each of a number of LFSR states;
- one or more sample output registers configured to store Ny bits of LFSR state sample information for each of a number of LFSR state samples;
- and
- one or more samplers comprising digital logic circuitry configured to:
- operatively couple sampled register cells of the one or more LFSRs to sample output register cells of the one or more sample output registers, wherein the sampled register cells are a subset of all register cells of the one or more LFSRs;
- and
- provide, to the sample output register cells, output bits derived from the bits of the sampled register cells.
4 more elements
An encoder, comprising:
- one or more linear feedback shift registers (LFSRs) configured to store N bits of LFSR state information for each of a number of LFSR states;
- one or more sample output registers configured to store Ny bits of LFSR state sample information for each of a number of LFSR state samples;
- and
- one or more samplers configured to reduce N bits of LFSR state information to Ny bits of LFSR state sample information,
- wherein the one or more LFSRs comprise at least a first and a second sampled register cells, the one or more sample output registers comprise at least a first and a second sample output register cells, and the one or more samplers comprises at least a first and a second digital logic circuitry, wherein:
- the first digital logic circuitry operatively couples the first sampled register cells to the first sample output registers cells;
- and
- the second digital logic circuitry operatively couples the second sampled register cells to the second sample output registers cells.
5 more elements
An encoder, comprising:
- one or more linear feedback shift registers (LFSRs) configured to store N bits of LFSR state information for each of a number of LFSR states;
- one or more sample output registers configured to store Ny bits of LFSR state sample information for each of a number of LFSR state samples;
- and
- one or more samplers configured to reduce N bits of LFSR state information to Ny bits of LFSR state sample information,
- wherein the one or more sample output registers are operatively coupled to a data bus configured to receive a serial bit stream of output bits of the one or more sample output registers.
2 more elements
A method of providing timing information for relating data, the method comprising:
- changing N bits of linear feedback shift register (LFSR) state responsive to one or more event intervals of a number of event intervals;
- reducing N bits of LFSR state information to Ny bits of LFSR state sample information responsive to the one or more event intervals, wherein Ny<N;
- and
- providing LFSR state sample information and event data responsive to the one or more event intervals.
1 more element
A method of providing timing information for relating data, the method comprising:
- changing N1 bits of first linear feedback shift register (LFSR) state and N2 bits of second LFSR state responsive to one or more event intervals of a number of event intervals;
- reducing N1 bits of LFSR state information to Ny1 bits of LFSR state sample information and reducing N2 bits of LFSR state information to Ny2 bits of LFSR state sample information, responsive to the one or more event intervals, wherein Ny1<N1 and Ny2<N2;
- and
- providing one or more LFSR state samples of reduced LFSR state information, responsive to the one or more event intervals.
1 more element
Dependencies are inferred from the claim text.