Signal quality in received wireless signals in the phase domain of shift keying demodulation

A method comprising:

• receiving, by a processing device, digital data, wherein the digital data comprises a systematic error as a linear function of residual carrier frequency offset (CFO) and phase noise (PN);
• extracting, by the processing device, first phase data from the digital data;
• determining, by the processing device in a phase domain, an estimate of the systematic error in the digital data using historical phase error data of additional digital data received prior to the digital data, wherein determining the estimate further comprises filtering the historical phase error data to remove an error in the estimate;
• generating, by the processing device, second phase data by adding or subtracting the estimate from the first phase data;
• determining, by the processing device, a set of symbols from the second phase data;
• and
• generating, by the processing device, a bit sequence of a data packet from the set of symbols.

A wireless device comprising:

• radio frequency front-end (RFFE) circuitry;
• a memory device;
• and
• a processing device coupled to the RFFE circuitry and the memory device, wherein the processing device comprises:
• a differential detection circuit to receive first digital data and generate second digital data by removing a carrier frequency offset (CFO), wherein the second digital data includes a systematic error caused by a residual CFO that is a linear function of the CFO and phase noise (PN);
• a phase extraction circuit to receive second digital data from the differential detection circuit and extract first phase data from the second digital data;
• phase estimation and correction logic to:
• receive the first phase data from the phase extraction circuit;
• determine a current phase error estimate for a first data packet;
• and
• generate second phase data by subtracting a historical phase error estimate from the first phase data;
• a data slicer to receive the second phase data from the phase estimation and correction logic and determine a set of symbols from the second phase data;
• and
• a bit-mapping circuit to receive the set of symbols from the data slicer and generate a bit sequence for the first data packet,
• wherein the phase estimation and correction logic is further to store a record in the memory device, the record comprising the current phase error estimate for the first data packet and a current receive signal strength indicator (RSSI) value for the first data packet.