US 11,082,267 B1 · Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter

Abstract

The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a set of TFFE coefficients from the original data signal. The method further comprises generating a time-domain-equalized altered data signal using the set of TFFE coefficients from the altered data signal. The method further comprises generating, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal at a voltage-feed forward equalization (VFFE) circuit using a set of VFFE coefficients.

Claims20

Dependent claims

A method for equalization of data signals, the method comprising:

receiving, by a first time-feed forward equalization (TFFE) circuit, an original data signal comprising original data bits and an enable signal comprising enable data bits;
receiving, by a second TFFE circuit, an altered data signal comprising altered data bits and an altered enable signal comprising altered enable bits;
generating, by the first TFFE circuit, from the original data signal and the enable signal, a time-domain-equalized original data signal using a set of TFFE coefficients;
generating, by the second TFFE circuit, from the altered data signal and the altered enable signal, a time-domain-equalized altered data signal using the set of TFFE coefficients;
and
generating, at a voltage-feed forward equalization (VFFE) circuit coupled to the first and second TFFE circuits, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal using a set of VFFE coefficients.

3 more elements

A programmable circuit for equalization of data signals, the circuit comprising:

a first time feed forward equalization (TFFE) circuit and a second TFFE circuit, the first and the second TFFE circuits configured to:
receive, by the first TFFE circuit, an original data signal comprising original data bits, and an enable signal comprising enable bits;
receive, by the second TFFE circuit, an altered data signal comprising altered data bits and an altered enable signal comprising altered enable bits;
generate, by the first TFFE circuit, from the original data signal and the altered data signal according to a set of TFFE coefficients, a time-domain-equalized original data signal;
and
generate, by the second TFFE circuit, from the altered data signal and the altered enable signal according to the set of TFFE coefficients, a time-domain-equalized altered data signal;
and
a voltage feed forward equalization (VFFE) circuit coupled to each of the TFFE circuits, the VFFE circuit configured to:
generate, from the time-domain-equalized original data signal and the time-domain-equalized altered data signal, a time-and-voltage-domain-equalized data signal according to a set of VFFE coefficients.

6 more elements

Dependencies are inferred from the claim text.

Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter

Life of this patent

Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter

Life of this patent

Abstract

Claims20