Transistor-based physically unclonable function
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus Lu
Life of this patent
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Abstract
An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.
Claims18
Physical unclonable function (PUF) circuitry, comprising:
- a difference generator circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor, the first PMOS transistor and the second PMOS transistor being configured to source a first current to provide an increasing first voltage at a first circuit node and a second current to provide an increasing second voltage at a second circuit node, respectively;
- a self-timed timing circuit configured to cause the first PMOS transistor and the second PMOS transistor to cease to source the first current and the second current, respectively, in response to the increasing first voltage or the increasing second voltage rising to a trigger voltage to trigger the self-timed timing circuit;
- and
- a sense amplifier configured to store a logical value indicating whether the first voltage is greater than or less than the second voltage in response to the increasing first voltage or the increasing second voltage rising to the trigger voltage.
Physical unclonable function (PUF) circuitry, comprising:
- a difference generator circuit having a first n-type metal-oxide-semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor and the second NMOS transistor being configured to sink a first current to provide a decreasing first voltage at a first circuit node and a second current to provide a decreasing second voltage at a second circuit node, respectively;
- a self-timed timing circuit configured to cause the first NMOS transistor and the second NMOS transistor to cease to sink the first current and the second current, respectively, in response to the decreasing first voltage or the decreasing second voltage falling to a trigger voltage to trigger the self-timed timing circuit;
- and
- a sense amplifier configured to store a logical value indicating whether the first voltage is greater than or less than the second voltage in response to the decreasing first voltage or the decreasing second voltage falling to the trigger voltage.
A method for determining an electronic signature of an electronic device, the method comprising:
- receiving a challenge for the electronic signature;
- sourcing, by a first p-type metal-oxide-semiconductor (PMOS) transistor of the electronic device and a second PMOS transistor of the electronic device, a first current to provide an increasing first voltage at a first circuit node of the electronic device and a second current to provide an increasing second voltage at a second circuit node of the electronic device, respectively;
- storing a first logical value indicating the first PMOS transistor is faster than the second PMOS transistor in response to the first voltage at the first circuit node rising to a trigger voltage before the second voltage at the second circuit node;
- storing a second logical value indicating the first PMOS transistor is slower than the second PMOS transistor in response to the first voltage at the first circuit node rising to the trigger voltage after the second voltage at the second circuit node;
- and
- providing the first logical value or the second logical value as a corresponding bit from among a plurality of bits of the electronic signature.
A method for determining an electronic signature of an electronic device, the method comprising:
- receiving a challenge for the electronic signature;
- sinking a first current to provide a decreasing first voltage at a first circuit node of the electronic device and a second current to provide a decreasing second voltage at a second circuit node of the electronic device, respectively;
- storing a first logical value indicating a first n-type metal-oxide-semiconductor (NMOS) transistor of the electronic device is faster than a second NMOS transistor of the electronic device in response to the first voltage at the first circuit node falling to a trigger voltage before the second voltage at the second circuit node;
- storing a second logical value indicating the first NMOS transistor is slower than the second NMOS transistor in response to the first voltage at the first circuit node falling to the trigger voltage after the second voltage at the second circuit node;
- and
- providing the first logical value or the second logical value as a corresponding bit from among a plurality of bits of the electronic signature.
Dependencies are inferred from the claim text.