US 11,082,159 B2Granted

Transmitter apparatus and signal processing method thereof

AssigneeSamsung Electronics Co., Ltd.

InventorsHong-sil Jeong, Se-ho Myung, Kyung-joong Kim

Life of this patent

Estimating the term…

Abstract

A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Claims5

Dependent claims

A receiving apparatus comprising:

a receiver configured to receive a signal from a transmitting apparatus;
a demodulator configured to demodulate the signal to generate values based on a 256-quadrature amplitude modulation (QAM);
a deinterleaver configured to split the values into a plurality of groups and deinterleave the plurality of groups;
and
a decoder configured to decode values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 12/15 and a code length of the LDPC code being 64800 bits,
wherein the plurality of groups are deinterleaved based on a following equation:
Yπ(j)=Xj for (0≤j<Ngroup),
where xj is a jth group among the plurality of groups, Yj is a jth group among the deinterleaved plurality of groups, Ngroup is a number of the plurality of groups, and π(j) denotes a deinterleaving order for the deinterleaving, and
wherein the π(j) is represented as follows:
Order of deinterleaving
π(j) (0 ≤ j < 180)
Code
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12/15
51
122
91
111
95
100
119
130
78
57
65
26
61
126
105
143
70
132
39
102
115
116
6
14
3
21
71
134
2
0
140
106
7
118
23
35
20
17
50
48
112
13
66
5
75
42
129
107
30
45
137
114
37
87
53
85
101
141
120
99
88
117
64
28
135
138
108
113
58
97
38
124
86
33
74
32
29
128
67
104
80
127
56
34
89
94
49
55
93
136
68
62
54
40
81
103
121
76
44
84
96
123
154
98
82
142
46
169
131
72
47
69
125
31
83
36
59
90
79
52
133
60
92
139
110
27
73
43
77
109
63
41
168
147
161
165
175
162
164
158
157
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150
171
167
145
151
153
9
155
170
146
166
149
15
159
11
176
152
156
144
148
172
178
24
22
179
4
163
174
173
19
10
177
12
16
1
8
18
25.

371 more elements

A transmitting apparatus comprising:

an encoder configured to encode input bits to generate parity bits based on a low density parity check (LDPC), a code rate of the LDPC code being 12/15 and a code length of the LDPC code being64800 bits;
an interleaver configured to interleave the parity bits, split a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups, and interleave the plurality of bit groups;
and
a mapper configured to map bits of the interleaved plurality of bit groups onto constellation points for 256-quadrature amplitude modulation (QAM),
wherein the plurality of bit groups are interleaved based on a following equation:
Yj=Xπ(j)(0≤j<Ngroup)
where xj is a j-th bit group among the plurality of bit groups, Yj is a j-th bit group among the interleaved plurality of bit groups, Ngroup is a number of the plurality of bit groups, and π(j) denotes an interleaving order for the interleaving, and
wherein the it(j) is represented as follows:
Order of deinterleaving
π(j) (0 ≤ j < 180)
Code
0
1
2
3
4
5
6
7
8
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10
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Rate
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164
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171
172
173
174
175
176
177
178
179
12/15
51
122
91
111
95
100
119
130
78
57
65
26
61
126
105
143
70
132
39
102
115
116
6
14
3
21
71
134
2
0
140
106
7
118
23
35
20
17
50
48
112
13
66
5
75
42
129
107
30
45
137
114
37
87
53
85
101
141
120
99
88
117
64
28
135
138
108
113
58
97
38
124
86
33
74
32
29
128
67
104
80
127
56
34
89
94
49
55
93
136
68
62
54
40
81
103
121
76
44
84
96
123
154
98
82
142
46
169
131
72
47
69
125
31
83
36
59
90
79
52
133
60
92
139
110
27
73
43
77
109
63
41
168
147
161
165
175
162
164
158
157
160
150
171
167
145
151
153
9
155
170
146
166
149
15
159
11
176
152
156
144
148
172
178
24
22
179
4
163
174
173
19
10
177
12
16
1
8
18
25.

370 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/424,481Filed 29 May 2019 · continuation
Priority: KR 10-2013-012566421 Oct 2013
Published: US 2019/0312680 A110 Oct 2019
Granted: 3 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

H04L 1/0071
Systems characterized by the type of code used: use of interleaving
H03M 13/11
Using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits: using multiple parity bits
H03M 13/1102
Using multiple parity bits: codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
H03M 13/1165
Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices: qC-LDPC codes as defined…

Family

Application61/843,114Us provisional application · filed 5 Jul 2013
Application61/864,758Us provisional application · filed 12 Aug 2013
Application61/897,480Us provisional application · filed 30 Oct 2013
Application14/324,436Parent of this continuation · filed 7 Jul 2014
Application15/264,057Parent of this continuation · filed 13 Sep 2016
US 9,484,957 B2Parent of this continuation · filed 1 Nov 2016
US 2019/0312680 A1Pre-grant publication · published 10 Oct 2019
US 10,367,606 B2Parent of this continuation
US 2015/0039973 A1Published application
US 2016/0380726 A1Published application
US 11,082,159 B2This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

Facts

Application

16/424,481Filed 29 May 2019 · continuation

Priority

KR 10-2013-012566421 Oct 2013

Published

US 2019/0312680 A110 Oct 2019

Granted

3 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification27 codes

H04L 1/0071
Systems characterized by the type of code used: use of interleaving
H03M 13/11
Using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits: using multiple parity bits
H03M 13/1102
Using multiple parity bits: codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
H03M 13/1165
Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices: qC-LDPC codes as defined…

Family

Application61/843,114Us provisional application · filed 5 Jul 2013

Application61/864,758Us provisional application · filed 12 Aug 2013

Application61/897,480Us provisional application · filed 30 Oct 2013

Application14/324,436Parent of this continuation · filed 7 Jul 2014

Application15/264,057Parent of this continuation · filed 13 Sep 2016

US 9,484,957 B2Parent of this continuation · filed 1 Nov 2016

US 2019/0312680 A1Pre-grant publication · published 10 Oct 2019

US 10,367,606 B2Parent of this continuation

US 2015/0039973 A1Published application

US 2016/0380726 A1Published application

US 11,082,159 B2This patent

From the US filing history. Foreign family members aren’t listed.