Hardware implementations of a quasi-cyclic syndrome decoder
AssigneeSK hynix Inc.
InventorsFan Zhang, Meysam Asadi, Xuanxuan Lu, Jianqing Chen
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AssigneeSK hynix Inc.
InventorsFan Zhang, Meysam Asadi, Xuanxuan Lu, Jianqing Chen
Estimating the term…
Disclosed are devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; and determining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword.
A method for reducing complexity of a decoder, comprising:
An apparatus for reducing complexity of a decoder, the apparatus comprising:
A non-transitory computer readable storage medium having instructions stored thereupon, the instructions, when executed by a processor, causing the processor to implement a method for reducing complexity of a decoder, comprising:
Dependencies are inferred from the claim text.