Beamforming using fractional time delay in digitally oversampled sensor systems, apparatuses, and methods

A system to time delay digital signals, comprising:

• a digital sensor responsive to an analog field quantity, the digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency;
• a first time delay element, the first time delay element is configured to receive as an input the oversampled digital output signal and to output a time delayed oversampled digital output signal, wherein the time delayed oversampled digital output signal is time delayed by a fractional delay, the fractional delay is equal to an integer number of sampling clock cycles times the sampling clock period;
• a filter, the filter is configured to receive as an input the time delayed oversampled digital output signal, the filter to low pass filter and to decimate to a lower sample rate the time delayed oversampled digital output signal and to output a low pass filtered decimated delayed digital output signal, wherein the lower sample rate is less than the sampling clock frequency;
• a second time delay element, the second time delay element is configured to receive, as an input, the low pass filtered decimated delayed digital output signal and to impart an integer delay, the integer delay is an integer number of cycles at the lower sample rate times the lower sampling rate period, the integer delay is applied to the low pass filtered decimated time delayed digital output signal;
• and
• a controller, the controller is configured to supply a control signal to set the fractional delay and the integer delay.

A system to time delay signals, comprising:

• a sensor element, the sensor element is responsive to an analog field quantity;
• a sigma-delta modulator, the sensor element is electrically coupled to the sigma-delta modulator and is configured to produce a pulse density modulated (PDM) output signal at a sampling clock frequency responsive to the analog field quantity;
• a first time delay element, the first time delay element is electrically configured to receive the PDM output signal, and to output a delayed PDM output signal, wherein the delayed PDM output signal is delayed by a fractional time delay equal to a number of cycles of the sampling clock frequency times a period of the sampling clock;
• a decimation module, the decimation module is configured to receive as an input the delayed PDM output signal, the decimation module to low pass filter and to decimate to a lower sample rate the delayed PDM output signal and to output a low pass filtered decimated delayed PDM output signal, wherein the lower sample rate is less than the sampling clock frequency, the decimation module to convert to pulse code modulation (PCM) format;
• a second time delay element, the second time delay element is configured to receive, as an input, the low pass filtered decimated delayed PDM output signal and to impart an integer delay, the integer delay is an integer number of cycles at the lower sample rate times a period at the lower sampling rate, the integer delay is applied to the low pass filtered decimated delayed PDM output signal;
• and
• a controller, the controller is configured to supply a control signal to set the fractional delay and the integer delay.

A decimation module for use in time delaying digital signals, comprising:

• a general number of N stages, the decimation module having as an input an oversampled digital output signal from a digital sensor;
• an ith stage, the ith stage to low pass filter and to decimate to an ith intermediate sampling rate an ith stage input signal to form an ith stage output signal, wherein the ith intermediate sample rating is less than a sampling clock frequency used to create the oversampled digital output signal;
• a first time delay element, the first time delay element to delay the ith stage output signal by a fractional time delay, wherein the fractional time delay is equal to an integer number of ith intermediate sampling rate cycles times the ith intermediate sampling rate period, the first time delay element to output a delayed ith stage output signal;
• an i+1 stage, the i+1 stage to receive as an i+1 stage input signal the delayed ith stage output signal, the i+1 stage to low pass filter and to decimate to an i+1 intermediate sampling rate the i+1 stage input signal to form an i+1 stage output signal, wherein the i+1 intermediate sampling rate is lower than the ith intermediate sampling rate;
• a second time delay element, the second time delay element is configured to receive, as an input, the i+1 stage output signal and to impart an integer delay, the integer delay is equal to an integer number of cycles at the i+1 intermediate sampling rate times the ith intermediate sampling rate period, the integer delay is applied to the i+1 stage output signal, the i+1 intermediate sampling rate is a baseband sampling rate, the i+1 stage output signal is an output signal from the decimation module that is time delayed by a combined time delay, the combined time delay is a sum of the fractional time delay and the integer time delay;
• and
• a controller, the controller is configured to supply a control signal to set the fractional time delay and the integer time delay.

A method to delay digital signals, comprising:

• sensing an analog field;
• outputting an oversampled digital signal responsive to the sensing, wherein the oversampled digital signal is created at a sampling clock rate:
• delaying the oversampled digital signal by a fractional time delay wherein the fractional time delay is equal to an integer number of sampling clock cycles to produce a delayed oversampled digital signal;
• applying a low pass filter with decimation to the delayed oversampled digital signal to output a baseband digital signal that is delayed by the fractional time delay;
• and
• delaying the baseband digital signal by an integer time delay, wherein the integer time delay is equal to a number of cycles at a baseband sampling rate times the baseband sampling rate period.

A non-transitory computer-readable storage medium storing program code for causing a data processing system to perform steps comprising:

• receiving signals from a digital sensor, the signals are responsive to an analog field;
• processing the signals to create an oversampled digital signal responsive to the receiving, wherein the oversampled digital signal is created at a sampling clock rate;
• and
• delaying the oversampled digital signal by a fractional time delay wherein the fractional time delay is equal to an integer number of sampling clock cycles times the sampling clock period to produce a delayed oversampled digital signal;
• applying a low pass filter with decimation to the delayed oversampled digital signal to output a baseband digital signal that is delayed by the fractional time delay;
• and
• delaying the baseband digital signal by an integer time delay, wherein the integer time delay is equal to a number of sampling clock cycles times the sampling clock period at a baseband sampling rate.

A system to delay digital signals, comprising:

• sensing means for measuring an analog field quantity;
• over sampling means, the over sampling means to over sample a signal detected by the sensing means resulting in an oversampled digital signal;
• fractional delaying means, the fractional delaying means to apply a fractional time delay to the oversampled digital signal, the fractional time delay is equal to an integer number of sampling clock cycles, resulting in a delayed oversampled digital signal;
• decimating means, the decimating means to receive the delayed oversampled digital signal and to low pass filter and to decimate to a lower sampling rate;
• integer delaying means, the integer delaying means to apply an integer time delay to the delayed oversampled digital signal, the integer time delay is a number of lower sampling rate cycles;
• and
• controlling means, the controlling means to adjust the fractional time delay and the integer time delay to establish a total time delay, wherein a resulting digital signal is delayed by a total time delay, wherein the total time delay is a sum of the fractional time delay and the integer time delay, and contains a digital representation of the analog field quantity without the noise introduced by the over sampling means.

A system to time delay digital signals, comprising:

• a digital sensor responsive to an analog field quantity, the digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency;
• a replicator, the replicator to receive the oversampled digital output signal and to output a first replica of the oversampled digital output signal and a second replica of the oversampled digital output signal;
• a first fractional time delay element, the first fractional time delay element is configured to receive as an input the first replica and to output a first time delayed oversampled digital output signal;
• a first filter, the first filter is configured to receive as an input the first time delayed oversampled digital output signal, the first filter to low pass filter and to decimate to a lower sample rate the first time delayed oversampled digital output signal and to output a first low pass filtered decimated delayed digital output signal, wherein the lower sample rate is less than the sampling clock frequency;
• a first integer time delay element, the first integer time delay element is configured to receive, as an input, the first low pass filtered decimated delayed digital output signal and to output a first time delayed digital output signal at the lower sample rate;
• a second fractional time delay element, the second fractional time delay element is configured to receive as an input the second replica and to output a second time delayed oversampled digital output signal;
• a second filter, the second filter is configured to receive as an input the second time delayed oversampled digital output signal, the second filter to low pass filter and to decimate to a lower sample rate the second time delayed oversampled digital output signal and to output a second low pass filtered decimated delayed digital output signal;
• and
• a second integer time delay element, the second integer time delay element is configured to receive, as an input, the second low pass filtered decimated delayed digital output signal and to output a second time delayed digital output signal at the lower sample rate.