Frequency lock loop circuits, low voltage dropout regulator circuits, and related methods

A gate driver integrated circuit comprising:

• a first die including a frequency lock loop (FLL) circuit, the FLL circuit including:
• clock divider circuitry producing a first clock signal having a first phase and a first frequency, and a second clock signal having a second phase and the first frequency, the first phase different from the second phase;
• and
• capacitor switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency;
• and
• a second die coupled to the first die, the second die including:
• driver circuitry having an output adapted to be coupled to a pass-gate transistor and configured to control the pass gate transistor based on the first frequency;
• and
• a low dropout circuit, the low dropout circuit to generate a pass-gate voltage based on an output voltage of the pass-gate transistor, the low dropout circuit to generate the pass-gate voltage in response to an output current of the pass-gate transistor satisfying a current threshold.