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US 11,082,051 B2Granted
Apparatus and methods for timing offset compensation in frequency synthesizers
AssigneeAnalog Devices Global Unlimited Company
InventorGordon John Allan
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Abstract
Apparatus and methods for timing offset compensation of frequency synthesizers are provided herein. In certain embodiments, an electronic system includes a frequency synthesizer, such as a fractional-N phase-locked loop (PLL), which generates an output clock signal based on timing of a reference clock signal. Additionally, the electronic system includes an integer PLL configured to compensate for a timing offset, such as a phase offset and/or frequency offset, of the frequency synthesizer based on timing of the output clock signal.
Claims20
A clock synthesis system with timing offset compensation, the clock synthesis system comprising:
- a frequency synthesizer configured to generate an output clock signal based on comparing timing of a reference clock signal to a first feedback signal, the output clock having a timing offset that is controllable by a phase adjustment signal, wherein the frequency synthesizer comprises:
- a control circuit including a digital accumulator configured to control the timing offset based on accumulating the phase adjustment signal,
- a feedback divider in a loop and configured to generate the first feedback signal, and
- a delta-sigma modulator configured to control a division rate of the feedback divider;
- and
- an integer phase-locked loop (PLL) configured to generate the phase adjustment signal based on comparing timing of the output clock signal of the frequency synthesizer to a timing reference, and to control the phase adjustment signal to compensate the frequency synthesizer for the timing offset, wherein the integer PLL comprises a phase detector configured to generate the phase adjustment signal by comparing the timing of the reference clock signal to a second feedback signal corresponding to the output clock signal.
3 more elements
An electronic system comprising:
- a first frequency synthesizer configured to generate a first output clock signal based on comparing timing of a reference clock signal to a first feedback signal, the first output clock signal having a timing offset relative to the reference clock signal that is controllable by a phase adjustment signal, wherein the first frequency synthesizer comprises:
- a control circuit including a digital accumulator configured to control the timing offset based on accumulating the phase adjustment signal,
- a feedback divider in a loop and configured to generate the first feedback signal, and
- a delta-sigma modulator configured to control a division rate of the feedback divider;
- and
- a first integer phase-locked loop (PLL) configured to generate the phase adjustment signal based on comparing timing of the first output clock signal to the timing of the reference clock signal, and to control the first frequency synthesizer with the phase adjustment signal to thereby compensate the first frequency synthesizer for the timing offset, wherein the first integer PLL comprises a phase detector configured to generate the phase adjustment signal by comparing the timing of the reference clock signal to a second feedback signal corresponding to the first output clock signal.
3 more elements
A method of timing offset compensation, the method comprising:
- synthesizing an output clock signal using a frequency synthesizer based on comparing timing of a reference clock signal to a first feedback signal, the output clock signal having a timing offset relative to the reference clock signal that is controllable by a phase adjustment signal, wherein the synthesizing of the output clock is further based on a control signal received from a control circuit including a digital accumulator configured to control the timing offset based on accumulating the phase adjustment signal, using a feedback divider in a loop to generate the first feedback signal, and using a delta-sigma modulator to control a division rate of the feedback divider;
- generating the phase adjustment signal based on comparing timing of the output clock signal to the timing of the reference clock signal using an integer phase-locked loop (PLL), wherein the integer PLL comprises a phase detector configured to generate the phase adjustment signal by comparing the timing of the reference clock signal to a second feedback signal corresponding to the output clock signal;
- and
- compensating for the timing offset using the phase adjustment signal.
1 more element
Dependencies are inferred from the claim text.