Clock distribution circuit using adjustable phase control and voltage converter including the same

A voltage converter comprising:

• a clock distribution circuit configured to generate a plurality of input clock signals, and adaptively adjust a phase of at least one of the plurality of input clock signals;
• and
• a plurality of switching regulators including a plurality of power switching nodes, the plurality of switching regulators configured to generate a plurality of output voltages based on the plurality of input clock signals,
• wherein the clock distribution circuit includes,
• a phase locked loop (PLL) configured to generate a plurality of reference clock signals,
• a first phase detecting and converting circuit configured to generate a plurality of input phase difference voltages based on phase differences between respective pairs of two reference clock signals among the plurality of reference clock signals,
• a second phase detecting and converting circuit configured to generate a plurality of output phase difference voltages based on phase differences between respective pairs of two power switching signals among a plurality of power switching signals received from the plurality of power switching nodes, and
• a clock generating and compensating circuit configured to generate the plurality of input clock signals by shifting phases of the plurality of reference clock signals, and control the phase of the at least one of the plurality of input clock signals based on the plurality of input phase difference voltages and the plurality of output phase difference voltages.

A clock distribution circuit comprising:

• a phase locked loop (PLL) configured to generate a first reference clock signal and a second reference clock signal;
• a first input phase-to-voltage converter (PVC) configured to generate a first input phase difference voltage based on a phase difference between the first reference clock signal and the second reference clock signal;
• a first output phase-to-voltage converter configured to generate a first output phase difference voltage based on a phase difference between a first power switching signal and a second power switching signal that are received from a first power switching node of a first external switching regulator and a second power switching node of a second external switching regulator, respectively, the first external switching regulator and the second external switching regulator being adjacent to each other;
• a first voltage-to-delay converter (VDC) configured to generate a first reference voltage based on an input reference voltage, and generate a first input clock signal to be provided to the first external switching regulator by shifting a phase of the first reference clock signal based on the first reference voltage;
• and
• a second voltage-to-delay converter configured to generate a second reference voltage based on the first reference voltage, generate a second input clock signal to be provided to the second external switching regulator by shifting a phase of the second reference clock signal based on the second reference voltage, and control a phase of the second input clock signal by adjusting a level of the second reference voltage based on the first input phase difference voltage and the first output phase difference voltage, and
• wherein the phase of the second input clock signal is adjusted such that the phase difference between the first power switching signal and the second power switching signal is equal to the phase difference between the first reference clock signal and the second reference clock signal.