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US 11,082,049 B2Granted
Semiconductor device
AssigneeSK hynix Inc.
InventorJayoung Kim
Life of this patent
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Abstract
A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.
Claims8
A semiconductor device comprising:
- a delayed clock generation circuit configured to generate a delayed clock by delaying a first input internal clock by a delay interval that is adjusted by a shifting code;
- a phase detection circuit configured to generate a detection signal by comparing phases of the delayed clock and a second input internal clock;
- a shifting control signal generation circuit configured to generate first to third shifting control signals for adjusting the shifting code, based on the first input internal clock and the detection signal;
- and
- a code latch circuit configured to generate a first delay code and a second delay code from the shifting code based on the first to third shifting control signals.
2 more elements
Dependencies are inferred from the claim text.