Integrated circuit including power gating cell
AssigneeSamsung Electronics Co., Ltd.
InventorsChanhee Park, Jongwoo Kim, Minsu Kim
Life of this patent
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Abstract
An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line and a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line.
Claims17
An integrated circuit comprising:
- a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line, wherein the power gating circuit comprises a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line, a second n-type transistor connected between the first power line and the first virtual power line, and a control circuit configured to provide switching signals to the transistors in response to a control signal;
- and
- a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit,
- wherein the control circuit is configured to adjust the switching signals to provide the first driving voltage of the power supply voltage during a power-on mode, the first driving voltage of a first retention voltage lower than the power supply voltage and higher than a ground voltage during a first retention mode, and the first driving voltage of a second retention voltage lower than the first retention voltage and higher than the ground voltage during a second retention mode,
- wherein a P-type metal-oxide-semiconductor (PMOS) area of the first P-type transistor is arranged between an N-type metal-oxide-semiconductor (NMOS) area of the first N-type transistor and an NMOS area of the second N-type transistor.
An integrated circuit comprising a first power gating cell configured to receive a power supply voltage from a first power line and to provide a first driving voltage to a logic cell through a first virtual power line, wherein the first power gating cell comprises:
- a first P-type metal-oxide-semiconductor (PMOS) area comprising a first p-type transistor connected between the first power line and the first virtual power line;
- a first N-type metal-oxide-semiconductor (NMOS) area comprising a first n-type transistor connected between the first power line and the first virtual power line;
- and
- a second NMOS area comprising a second n-type transistor connected between the first power line and the first virtual power line, and
- wherein the first PMOS area comprises an n well doped with n-type impurities and extending in a first direction,
- wherein the first PMOS area is arranged between the first NMOS area and the second NMOS area.
An integrated circuit comprising a first power gating cell for receiving a ground voltage from a ground line and providing a driving voltage to a logic cell through a virtual ground line, wherein the first power gating cell comprises:
- a first N-type metal-oxide-semiconductor (NMOS) area comprising a first n-type transistor connected between the ground line and the virtual ground line;
- a first P-type metal-oxide-semiconductor (PMOS) area comprising a first p-type transistor connected between the ground line and the virtual ground line is formed;
- and
- a second PMOS area comprising a second p-type transistor connected between the ground line and the virtual ground line, and
- wherein the first PMOS area is located in an n well doped with n-type impurities and extending in a first direction,
- wherein the first NMOS area is arranged between the first PMOS area and the second PMOS area.
Dependencies are inferred from the claim text.