Duty cycle correction circuit

A duty cycle correction circuit, comprising:

• a first inverter comprising an input terminal and an output terminal, the input terminal of the first inverter being configured to receive a first signal, and the output terminal of the first inverter being configured to output a third signal, the third signal being an inverted signal of the first signal and having a first delay time relative to the first signal;
• a first adjustment circuit comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first adjustment circuit being connected to the output terminal of the first inverter and configured to receive the third signal, and the output terminal of the first adjustment circuit being configured to output a first correction signal;
• and
• a first delayer, an input terminal of the first delayer being configured to receive a second signal, a cycle length of the second signal being equal to a cycle length of the first signal and a phase of the second signal being different from a phase of the first signal by ½ of the cycle length, and an output terminal of the first delayer being connected to the second input terminal of the first adjustment circuit and configured to output a fourth signal to the first adjustment circuit, the fourth signal having the first delay time relative to the second signal;
• wherein the first correction signal is at a high level when the third signal and the fourth signal are at the high level, and the first correction signal is at a low level when the third signal and the fourth signal are at the low level.