Memory interface system for duty-cycle error detection and correction
AssigneeSanDiskTechnologies LLC
InventorsGilad Marko, Arkady Katz
Life of this patent
Estimating the term…
Abstract
A method for duty cycle error detection and correction includes receiving, during a read operation performed on a memory cell, a first data strobe signal. The method also includes generating a second data strobe signal by phase delaying the first data strobe signal. The method also includes determining, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted. The method also includes adjusting a clock signal based on a determination that the duty cycle is distorted.
Claims20
A method for duty cycle distortion detection and correction, the method comprising:
- receiving, during a read operation performed on a memory cell, a first data strobe signal;
- generating a second data strobe signal by phase delaying the first data strobe signal;
- determining, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted;
- and
- adjusting a clock signal based on a determination that the duty cycle is distorted.
A controller comprising:
- a bus interface in communication with one or more memory blocks of a memory system;
- and
- a processor configured to:
- receive, during a read operation performed on at least one memory cell of the one or more memory blocks, a first data strobe signal;
- generate a second data strobe signal by phase delaying the first data strobe signal;
- determine, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted;
- and
- adjust a clock signal based on a determination that the duty cycle is distorted.
A system for detecting and correcting duty cycle distortion, the system comprising:
- at least one memory device;
- and
- a controller in communication with the at least one memory device, the controller including:
- a duty cycle detector configured to:
- receive, during a read operation performed on the at least one memory device, a first data strobe signal from the at least one memory device;
- generate a second data strobe signal by phase delaying the first data strobe signal;
- and
- determine, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted;
- a duty cycle correction circuit configured to:
- receive a signal from the duty cycle detector indicating whether the duty cycle is distorted;
- determine, in response to the signal from the duty cycle detector indicating that the duty cycle is distorted, whether the duty cycle is above a duty cycle threshold;
- and
- decrease a clock signal based on a determination that the duty cycle is above the duty cycle threshold;
- and
- a duty cycle connection circuit configured to communicate the clock signal to the at least one memory device.
Dependencies are inferred from the claim text.