Digitally controlled delay line circuit and method

A digitally controlled delay line (DCDL) comprising:

• an input terminal;
• an output terminal;
• and
• a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal, each stage of the plurality of stages comprising:
• a first inverter configured to selectively propagate the signal along the first signal path;
• a second inverter configured to selectively propagate the signal along the second signal path;
• and
• third and fourth inverters coupled in series and configured to selectively propagate the signal from the first signal path to the second signal path.

A method of controlling a signal delay time, the method comprising:

• receiving an input signal at a first stage of a plurality of sequentially coupled stages of a digitally controlled delay line (DCDL);
• and
• selecting a second stage of the plurality of sequentially coupled stages as a return stage, thereby activating a first tunable inverter of the second stage coupled between a first signal path of a signal delay path of the DCDL and a second signal path of the signal delay path of the DCDL,
• wherein the selecting the second stage of the plurality of sequentially coupled stages as the return stage comprises one of:
• activating two tristate inverters of the first stage as part of the first signal path and two tristate inverters of the first stage as part of the second signal path;
• or
• activating a second tunable inverter of the second stage coupled in series with the first tunable inverter between the first signal path and the second signal path.