Highly linear input and output rail-to-rail amplifier

#The paper of J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. Ausin, “Constant-constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1364-1372, August 2003 (hereinafter “Carrillo Paper”), which is incorporated by reference herein in its entirety for all purposes, describes “a general purpose low-voltage rail-to-rail input stage” that “provides constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation.” A shortcoming of the circuit described in the Carrillo Paper is that it may not provide the linearity performance needed in some applications.

#In one embodiment, the present disclosure provides a method for maintaining a constant bias current across a voltage swing of an input signal received by input transconductors of an amplifier. The method includes generating a supply side current mirror gate voltage as a function of input signal voltage and using the gate voltage for controlling bias current sources to the input transconductors, wherein a bias current of the input transconductors is maintained as constant.

#In another embodiment, the present disclosure provides an apparatus comprising an amplifier that includes input transconductors that receive an input signal, the input signal having a voltage swing. The amplifier also includes a supply side current mirror that generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal.

#FIG. 1 is a diagram illustrating a subsystem that employs an amplifier that exhibits highly linear input and output rail-to-rail characteristics in accordance with embodiments of the present disclosure.

#FIG. 2 is a circuit diagram illustrating portions of a highly linear input and output rail-to-rail amplifier in accordance with embodiments of the present disclosure.

#FIG. 3 is a circuit diagram illustrating portions of a highly linear input and output rail-to-rail amplifier in accordance with embodiments of the present disclosure.

#Referring now to FIG. 1, a diagram illustrating a subsystem 100 that employs an amplifier 102 that exhibits highly linear input and output rail-to-rail characteristics in accordance with embodiments of the present disclosure is shown. An application processor (not shown) drives pulse-code modulation (PCM) data to a digital-to-analog converter (DAC) 104. The DAC 104 converts the PCM data into an analog differential voltage which an amplifier 106 converts to an analog single-ended excitation out voltage VEXO. The excitation out voltage VEXO is provided to a first analog-to-digital converter (ADC1) 108 and to a pin EXOUT, which is also coupled to an external load which may be modelled by a parallel combination of a resistor R1 and capacitor C1. The excitation out voltage VEXO value may be read from ADC1 108 and processed as desired. The excitation out voltage VEXO is coupled to a non-inverting input of the amplifier 102, which amplifies the excitation out voltage VEXO. The excitation out voltage VEXO is amplified by the amplifier 102 and copied to a node VSNS that is coupled to an inverting input of the amplifier 102 and a pin SENSE. A capacitor Cp is coupled between pin SENSE and ground.

#The excitation out voltage VEXO excites a passive sensor 112 that produces a current ISNS. The current ISNS may be sensed through pin SENSE at node VSNS and processed as desired. A resistor network is coupled between node VSNS and a node VTIAO. Node VTIAO is coupled to the output of the amplifier 102 and a pin TIAOUT. Node VTIAO is sensed by a second ADC 118. The excitation out voltage VEXO is amplified onto node VTIAO. The flow of current generated by the amplifier 102 through the feedback resistor network produces the voltage at node VTIAO.

#Advantageously, as described in more detail below, the amplifier 102 is a highly linear input and output rail-to-rail amplifier. More specifically, the amplifier 102 includes improvements over conventional amplifiers (e.g., over the amplifier of Carrillo) to improve its linearity and thereby reduce its total harmonic distortion (THD). In one embodiment, the amplifier 102 input ranges from zero to 3 volts, and the open-loop gain of the amplifier 102 is approximately 80 dB. In the example embodiment of FIG. 1, the resistor network comprises a variable resistor Rf in parallel with a variable capacitor CEXT. In one embodiment, the passive sensor 112 comprises a resistor RSNS in parallel with a capacitor CSNS coupled between ground and node VSNS. The embodiment of FIG. 1 also includes a capacitor CS coupled between the passive sensor 112 and node VSNS. In one embodiment, the passive sensor 112 is off-chip relative to the rest of the subsystem 100.