Self-adaptive synchronous rectification control system and method of active clamp flyback converter

A self-adaptive synchronous rectification control system of an active clamp flyback converter, comprising:

• a sampling and signal processing circuit,
• a control circuit with a microcontroller as a core, and
• a gate driver,
• wherein an input end of the sampling and signal processing circuit is connected with a drain of a secondary synchronous rectifier of the active clamp flyback converter, a first output end and a second output end of the sampling and signal processing circuit are both connected with the control circuit with the microcontroller, an output end of the control circuit with the microcontroller is connected with an input end of the gate driver, and an output end of the gate driver is connected with a gate of the secondary synchronous rectifier of the active clamp flyback converter;
• wherein,
• the control circuit with the microcontroller comprises:
• a first comparator,
• a second comparator,
• a counter,
• a register,
• a control unit, and
• a pulse width modulation (PWM) timer,
• wherein the first comparator, the second comparator and the PWM timer are actual hardware function modules inside the microcontroller, the counter, the register and the control unit are software function modules implemented on a hardware basis of the microcontroller, a first sensing voltage signal outputted by the first output end of the sampling and signal processing circuit is connected with an inverting input end of the first comparator, a second sensing voltage signal outputted by the second output end of the sampling and signal processing circuit is connected with an inverting input end of the second comparator, non-inverting input ends of the first comparator and the second comparator are both connected with the control unit, and an output signal A of the first comparator is connected with a first input end of the register;
• an output signal B of the second comparator is connected with an input end of the counter, the counter records high and low level change times N of the output end signal B of the second comparator, and an output signal N of the counter is connected with a second input end of the register;
• the first output end and the second output end of the register are both connected with the control unit;
• an output signal of the control unit is connected with the PWM timer;
• and an output signal of the PWM timer is connected with the gate driver.