Timer for power converter controller
AssigneeTexas Instruments Incorporated
InventorAnmol Sharma
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosure provide for a circuit. In an example, the circuit includes an input circuit having a first output and a second output, a first timer having a first input coupled to the first output of the input circuit, a second timer having a first input coupled to the second output of the input circuit, a second input coupled to an output of the first timer, and an output coupled to a second input of the first timer, and an output circuit coupled to the output of the first timer and the output of the second timer.
Claims15
A switched mode power supply (SMPS), comprising:
- a power converter having an output;
- and
- a controller, that includes:
- a loop controller having an input coupled to the output of the power converter, and having an output that is a control signal responsive to an electrical characteristic of the power converter;
- a predictive timer having an input coupled to the output of the loop controller and adapted to independently determine an on-time (TON) and an off-time (TOFF) for at least some power transistors of the power converter;
- and
- a gate driver having an input coupled to the output of the predictive timer and having an output coupled to the power converter and adapted to control the power converter responsive to the determined TON and the determined TOFF;
- and
- wherein the predictive timer is configured to:
- start a first timer and a second timer at a first edge transition of a control signal provided by the gate driver to control some power transistors of the power converter;
- pause the second timer at an expiration of the first timer;
- resume the second timer at a second edge transition of the control signal provided by the gate driver to control some power transistors of the power converter;
- and initiate a third edge transition of the control signal provided by the gate driver at an expiration of the second timer.
A method, comprising:
- receiving signals for use in calculating an on-time (TON) and an off-time (TOFF);
- controlling a first timer and a second timer to begin counting at an edge transition of a control signal for controlling some power transistors of a power converter;
- controlling the second timer to pause counting at an expiration of the first timer;
- controlling the second timer to resume counting at another edge transition of the control signal for controlling some power transistors of the power converter;
- controlling the first timer to resume counting at an expiration of the second timer;
- and
- generating an output signal based on an output of the first timer and the second timer.
A controller, comprising:
- a loop controller having an input configured to be coupled to an output of a power converter, the loop controller having an output that is a control signal responsive to the output of the power converter;
- a predictive timer having an input coupled to the output of the loop controller and adapted to independently determine an on-time (TON) and an off-time (TOFF) for at least some power transistors by:
- starting a first timer and a second timer at a first edge transition of a control signal provided by a gate driver to control some power transistors of the power converter;
- pausing the second timer at an expiration of the first timer;
- resuming the second timer at a second edge transition of the control signal;
- and
- initiating a third edge transition of the control signal at an expiration of the second timer;
- and
- the gate driver having an input coupled to the output of the predictive timer.
Dependencies are inferred from the claim text.