Via structure with low resistivity and method for forming the same

A semiconductor device structure, comprising:

• an insulating layer over a substrate;
• a gate structure formed in the insulating layer, comprising:
• a gate electrode layer;
• a conductive capping layer formed over the gate electrode layer;
• a gate dielectric layer formed on a sidewall of the gate electrode layer;
• and
• a gate spacer formed on a sidewall of the gate dielectric layer, wherein the gate spacer has an upper surface that is substantially level with an upper surface of the gate dielectric layer and protrudes above an upper surface of the conductive capping layer;
• a first via structure in direct contact with the conductive capping layer;
• and
• a second via structure electrically connected to a source/drain feature in the substrate, wherein a lower surface of the first via structure is below a lower surface of the second via structure.

A method for forming a semiconductor device structure, comprising:

• forming a first insulating layer over a substrate;
• forming a gate spacer in the first insulating layer;
• forming a gate electrode layer in the first insulating layer and adjacent to the gate spacer;
• covering the gate electrode layer with an insulating capping layer, wherein an entirety of a lower surface of the insulating capping layer is above the gate electrode layer;
• etching the first insulating layer using the insulating capping layer as an etch mask, so as to form an opening that exposes a source/drain feature in the substrate;
• forming a contact structure in the opening, wherein the contact structure has an upper surface that is substantially level with an upper surface of the insulating capping layer, and a sidewall that is in direct contact with the gate spacer;
• forming a first via structure in the insulating capping layer and electrically connected to the gate electrode layer;
• and
• forming a second via structure over and electrically connected to the source/drain feature via the contact structure.