Insulated gate bipolar transistor device and method for manufacturing the same

An insulated gate bipolar transistor device, comprising:

• a collector electrode located at the bottom of the device;
• a first semiconductor layer of a first conduction type located above the collector electrode;
• a second semiconductor drift region of a second conduction type located above the first semiconductor layer;
• at least one periodically arranged trench regions located on an upper surface of the second semiconductor drift region, at least one trenches extending from the upper surface of the second semiconductor drift region into the second semiconductor drift region being provided in each trench region, a gate electrode being provided in each trench, and the gate electrode being isolated from an inner wall of the corresponding trench;
• and
• an emitter electrode located on the top of the device;
• wherein,
• the trench region comprises a cell zone, a transitional cell zone, and a pseudo cell zone from outside to inside, and a trench arrangement density in the pseudo cell zone is less than a trench arrangement density in the cell zone, and a trench arrangement density in the transitional cell zone;
• wherein trenches in the transitional cell zone and the pseudo cell zone are configured to be pseudo gate trenches, each pseudo gate trench is filled with a pseudo gate electrode, and the pseudo gate electrode is connected to the emitter electrode;
• wherein a ninth semiconductor buried layer region of the second conduction type is provided between the second semiconductor drift region and the third semiconductor region, and an average doping concentration of the ninth semiconductor buried layer region is greater than a doping concentration of the second semiconductor drift region;
• wherein a tenth semiconductor buried layer region of the second conduction type is provided between the second semiconductor drift region and the sixth semiconductor region, and an average doping concentration of the tenth semiconductor buried layer region is greater than the doping concentration of the second semiconductor drift region and less than the average doping concentration of the ninth semiconductor buried layer region.