Protective bilayer inner spacer for nanosheet devices

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of first semiconductor layers alternately stacked with a plurality of second semiconductor layers on a semiconductor substrate;
• laterally recessing the plurality of first semiconductor layers with respect to the plurality of second semiconductor layers to form a plurality of vacant areas on lateral sides of the plurality of first semiconductor layers;
• forming a plurality of first inner spacers on the lateral sides of the plurality of first semiconductor layers in respective ones of the plurality of vacant areas;
• forming a plurality of second inner spacers on sides of the plurality of first inner spacers in the respective ones of the plurality of vacant areas;
• laterally recessing the plurality of second semiconductor layers;
• and
• growing a plurality of source/drain regions from the plurality of second semiconductor layers;
• wherein forming the plurality of first inner spacers comprises:
• depositing a first inner spacer material to fill in respective ones of the plurality of vacant areas;
• and
• etching the deposited first inner spacer material to remove a portion of the deposited first inner spacer material from the filled-in respective ones of the plurality of vacant areas.

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of sacrificial semiconductor layers alternately stacked with a plurality of channel semiconductor layers on a semiconductor substrate;
• laterally recessing the plurality of sacrificial semiconductor layers with respect to the plurality of channel semiconductor layers to form a plurality of vacant areas on lateral sides of the plurality of sacrificial semiconductor layers;
• forming a plurality of first inner spacers on the lateral sides of the plurality of sacrificial semiconductor layers in respective ones of the plurality of vacant areas;
• forming a plurality of second inner spacers on sides of the plurality of first inner spacers in the respective ones of the plurality of vacant areas;
• laterally recessing the plurality of channel semiconductor layers;
• growing a plurality of source/drain regions from the plurality of channel semiconductor layers;
• removing the plurality of sacrificial semiconductor layers;
• removing the plurality of first inner spacers;
• and
• forming a plurality of gate structures in place of the removed plurality of sacrificial semiconductor layers and the removed plurality of first inner spacers.