Self-aligned contacts for vertical field effect transistors
AssigneeInternational Business Machines Corporation
InventorsSu Chen Fan, Ekmini A. De Silva, Sivananda K. Kanakasabapathy
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Abstract
Semiconductor devices and methods of forming the same include forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region. An encapsulating material is selectively deposited over the gate stack, leaving the bottom spacer exposed. An inter-layer dielectric is formed over the encapsulating material. A via is formed in the inter-layer dielectric to contact the bottom source/drain layer.
Claims13
A method for forming a semiconductor device, comprising:
- forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region;
- selectively depositing an encapsulating material over the gate stack, leaving an upper surface of the bottom spacer exposed;
- forming an inter-layer dielectric over the encapsulating material;
- and
- forming a via in the inter-layer dielectric to contact the bottom source/drain region.
A method for forming a semiconductor device, comprising:
- forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region;
- selectively depositing an encapsulating material over the gate stack, leaving the bottom spacer exposed, comprising:
- forming a self-assembled monolayer that selectively attaches to an upper surface of the bottom spacer;
- and
- depositing encapsulating material that does not adhere to the self-assembled monolayer;
- forming an inter-layer dielectric over the encapsulating material;
- and
- forming a via in the inter-layer dielectric to contact the bottom source/drain region.
Dependencies are inferred from the claim text.