Formation of silicide contacts in semiconductor devices

A semiconductor device comprising:

• a substrate having a n-type field effect transistor (nFET) region and a p-type FET (pFET) region;
• an n-type source and drain (S/D) region in the nFET region, the n-type S/D region having a first crystalline structure;
• a first silicide region embedded in a top portion of the n-type S/D region, the first silicide region comprising nickel silicide and having a first thickness, wherein sidewalls and a bottom surface of the first silicide region directly contact material of the n-type S/D region;
• a p-type S/D region in the pFET region, the p-type S/D region having a second crystalline structure, wherein the p-type S/D region is free of amorphous silicon germanium;
• a second silicide region embedded in a top portion of the p-type S/D region, the second silicide region comprising nickel silicide, nickel germanide (NiGe), and nickel germanosilicide (NiSiGe) and having a second thickness different than the first thickness, wherein sidewalls and a bottom surface of the second silicide region directly contact material of the p-type S/D region;
• a contact trench extending through an interlayer dielectric layer to the first silicide region;
• a dielectric sidewall spacer extending along a sidewall of the contact trench to the first silicide region such that a first portion of a top surface of the first silicide region is in direct contact with and covered by the dielectric sidewall spacer and a second portion of the top surface of the first silicide region is free of the dielectric sidewall spacer;
• and
• a contact feature disposed within the contact trench and in direct contact with both the dielectric sidewall spacer and the second portion of the top surface of the first silicide region,
• wherein a difference in thickness between the first silicide region and the second silicide region is less than 20 angstroms (A),
• wherein the n-type S/D region and the p-type S/D region further comprise a same implant species selected from the group consisting of C, Sn, Pb, and Al.

A device comprising:

• a substrate including a n-type field effect transistor (nFET) region and a p-type FET (pFET) region, wherein the nFET region and the pFET region are separated by an isolation feature;
• an n-type source and drain (S/D) region in the nFET region, wherein the n-type S/D region comprises a first silicide feature disposed therein, the n-type S/D region having a first crystalline structure, the first silicide feature including nickel silicide, wherein the first silicide feature directly contacts material of the n-type S/D region;
• a p-type S/D region in the pFET region, wherein the p-type S/D region comprises a second silicide feature disposed therein, the p-type S/D region having a second crystalline structure, the second silicide feature including nickel germanosilicide (NiSiGe), wherein the second silicide feature directly contacts material of the p-type S/D region, wherein the p-type S/D region is free of amorphous silicon germanium;
• a first contact trench extending through an interlayer dielectric layer to the first silicide feature, wherein a bottommost surface of the interlayer dielectric layer facing the substrate physically contacts a first portion of the substrate including the first silicide feature, and wherein the bottommost surface of the interlayer dielectric layer facing the substrate physically contacts a second portion of the substrate extending from an edge of the first silicide feature to an edge of an interface between the substrate and a gate spacer disposed thereon, wherein the second portion of the substrate is free of amorphous silicide;
• a first dielectric sidewall spacer extending along a sidewall of the first contact trench to the first silicide feature such that a first portion of a top surface of the first silicide feature is in direct contact with and covered by the first dielectric sidewall spacer and a second portion of the top surface of the first silicide feature is free of the first dielectric sidewall spacer;
• and
• a first contact feature disposed within the first contact trench and in direct contact with the first dielectric sidewall spacer and the second portion of a top surface of the first silicide feature,
• wherein the first silicide feature has a first thickness, the second silicide feature has a second thickness different than the first thickness, and both the first thickness and the second thickness are greater than 100 A, and
• wherein a difference between the first thickness and the second thickness is less than 20 A.