Field-effect transistors with vertically-serpentine gates
AssigneeGlobalFoundries U.S. Inc.
InventorsSteven M. Shank, Anthony K. Stamper, Siva P. Adusumilli
Life of this patent
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Abstract
Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.
Claims15
A structure, comprising:
- an active device region comprised of a semiconductor material, the active device region including a top surface, a first trench defining a first recess in the semiconductor material, and a second trench defining a second recess in the semiconductor material, the first trench including a first bottom surface and a first sidewall extending from the first bottom surface to the top surface, and the second trench including a second bottom surface and a second sidewall extending from the second bottom surface to the top surface;
- a plurality of shallow trench isolation regions arranged to surround the active device region, the first trench, and the second trench;
- a first gate electrode having a first section on the semiconductor material at the top surface of the active device region, a second section on the semiconductor material at the first bottom surface of the first trench, and a third section on the semiconductor material at the first sidewall of the first trench;
- and
- a second gate electrode having a first section on the semiconductor material at the top surface of the active device region, a second section on the semiconductor material at the second bottom surface of the second trench, and a third section on the semiconductor material at the second sidewall of the second trench,
- wherein the second gate electrode is arranged substantially parallel to the first gate electrode.
A method, comprising:
- patterning a first trench defining a first recess in a semiconductor material of an active device region, wherein the first trench includes a first bottom surface and a first sidewall extending from the first bottom surface to a top surface of the active device region;
- patterning a second trench defining a second recess in the semiconductor material of the active device region, wherein the second trench includes a second bottom surface and a second sidewall extending from the second bottom surface to the top surface of the active device region;
- forming a plurality of shallow trench isolation regions that are arranged to surround the active device region, the first trench, and the second trench;
- forming a first gate electrode having a first section on the top surface of the active device region, a second section on the first bottom surface of the first trench, and a third section on the first sidewall of the first trench;
- and
- forming a second gate electrode having a first section on the top surface of the active device region, a second section on the second bottom surface of the second trench, and a third section on the second sidewall of the second trench,
- wherein the second gate electrode is arranged substantially parallel to the first gate electrode.
Dependencies are inferred from the claim text.