LDMOS with high-k drain STI dielectric
AssigneeTexas Instruments Incorporated
InventorsUmamaheswari Aghoram, Pushpa Mahalingam, Alexei Sadovnikov, Eugene C Davis
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Abstract
A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.
Claims22
A laterally diffused metal oxide silicon (LDMOS) transistor comprising:
- a drain drift region formed in a substrate and containing a drain contact region;
- a gate structure overlying a channel region in the substrate;
- a first shallow-trench isolation (STI) structure formed between the drain contact region and the channel region, the first STI structure comprising a high-k dielectric;
- a second STI structure comprising silicon dioxide that touches the drain contact region;
- and
- a double-diffused well (DWELL) within the channel region, the first STI structure extending from the drain contact region to the DWELL.
An integrated circuit comprising:
- a laterally diffused metal oxide silicon (LDMOS) transistor, including:
- a source region formed in a substrate;
- a drain drift region formed in the substrate and containing a drain contact region;
- a gate structure overlying a double-diffused well (DWELL) between the source region and drain contact region;
- a gate dielectric separating the gate structure from the channel region, the gate dielectric comprising silicon dioxide;
- a high-k STI structure touching the drain contact region and extending under the gate structure toward the DWELL;
- and
- a silicon oxide STI structure touching the drain contact region and extending away from the high-k STI structure.
An electronic device, comprising:
- an n-well within a semiconductor substrate;
- first and second shallow trench isolation (STI) structures within the n-well, the first STI structure including a high-k dielectric and the second STI structure including silicon oxide;
- a gate electrode over the semiconductor substrate and extending partially over the n-well and the first STI structure;
- an n+ region within the n-well and touching both the first and second STI structures;
- and
- a double-diffused well (DWELL) touching the first STI structure.
An electronic device, comprising:
- an n-well within a semiconductor substrate;
- first and second shallow trench isolation (STI) structures within the n-well, the first STI structure including a high-k dielectric and the second STI structure including silicon oxide;
- a gate electrode over the semiconductor substrate and extending partially over the n-well and the first STI structure;
- and
- an n+ region within the n-well and touching both the first and second STI structures,
- wherein the first STI structure has a first top surface and the second STI structure has a second top surface, the first top surface being higher above a top surface of the semiconductor substrate than the second top surface.
Dependencies are inferred from the claim text.