Semiconductor devices and fabrication methods thereof

A method for fabricating a semiconductor device, comprising:

• providing a semiconductor structure including a semiconductor substrate, a plurality of semiconductor fin structures formed on the semiconductor substrate, a liner insulation layer formed on the semiconductor substrate and sidewalls of each semiconductor fin structure of the plurality of the semiconductor fin structures, and a trench insulation layer formed on the semiconductor substrate and surrounding each semiconductor fin structure of the plurality of the semiconductor fin structures, wherein the plurality of semiconductor fin structures include a plurality of first semiconductor fin structures and a plurality of second semiconductor fin structures, the trench insulation layer is formed on the liner insulation layer, and a top surface of the trench insulation layer is leveled with a top surface of the semiconductor fin structures;
• performing a first anti-punch-through doping process on the plurality of first semiconductor fin structures to form a first anti-punch-through region in each first semiconductor fin structure;
• removing a portion of each second semiconductor fin structure to form a trench to expose sidewalls of a top portion of the liner insulation layer;
• forming a semiconductor layer on the remaining portion of each second semiconductor fin structure and on the sidewalls of the top portion of the liner insulation layer;
• forming a second anti-punch-through region by performing a second anti-punch-through doping process on the semiconductor layer to convert the semiconductor layer to the second anti-punch-through doping region;
• performing an annealing process on the second anti-punch-through region;
• after performing the annealing process, forming a channel layer on the second anti-punch-through region and on the sidewalk of the top portion of the liner insulation layer;
• and
• performing an etching process on the trench insulation layer and the liner insulation layer to expose a portion of the plurality of first semiconductor fin structures over the first anti-punch-through region and a portion of the channel layer, a remaining portion of the plurality of first semiconductor fin structures over the first anti-punch-through region and a remaining portion of the channel layer being left covered by a remaining portion of the trench insulation layer and liner insulation laver.