Multi-spheroid BEOL capacitor
AssigneeInternational Business Machines Corporation
InventorsAlexander Reznicek, Praneet Adusumilli, Shanti Pancharatnam, Oscar Van Der Straten
Life of this patent
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Abstract
Method and apparatus for a capacitive structure. The capacitive structure includes a material stack having a deep trench formed therein. The material stack includes alternating vertical and semi-ovoid sidewall surfaces. The material stack further includes alternating metallization layers and dielectric layers. At least one of the semi-spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers in the deep trench. At least one of the vertical sidewall surfaces is a sidewall surface of at least one metallization layer in the deep trench.
Claims6
A capacitive structure comprising:
- a material stack having a trench formed therein, the material stack comprising alternating vertical and semi-spheroidal sidewall surfaces, wherein the material stack includes alternating metallization layers and dielectric layers, wherein at least one of the semi-spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers in the trench, and wherein at least one of the vertical sidewall surfaces is a sidewall surface of at least one metallization layer in the trench;
- a first conductive layer made of a diffusion barrier material and a reflow enhancement layer deposited overlying the semi-spheroidal sidewall surfaces and the vertical sidewall surfaces of the trench;
- a capacitive dielectric material layer deposited overlying the first conductive layer;
- a second conductive layer deposited overlying the capacitive dielectric material layer;
- a third conductive material filling in the remaining portion of the trench overlying the entirety of the second conductive layer;
- and
- a trench contact formed in a remaining portion of the material stack not including the trench and at least one shallow trench contact in the third conductive material.
A semiconductor structure comprising:
- a front-of-the-line semiconductor (FEOL) circuit layer;
- and
- a back-of-the-line (BEOL) capacitor having a trench formed in a material stack comprising alternating vertical and semi-spheroidal sidewall surfaces, wherein the material stack includes alternating metallization layers and dielectric layers, wherein at least one of the semi spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers at the trench, wherein at least one of the vertical sidewall surfaces is formed in a sidewall surface of at least one metallization layer at the trench, and wherein the material stack overlies the FEOL circuit layer;
- a first conductive layer made of a diffusion barrier material and a reflow enhancement layer deposited overlying the semi-spheroidal sidewall surfaces and the vertical sidewall surfaces of the trench;
- a capacitive dielectric material layer deposited overlying the first conductive layer;
- a second conductive layer deposited overlying the capacitive dielectric material layer;
- a third conductive material filling in the remaining portion of the trench overlying the entirety of the second conductive layer;
- and
- a trench contact formed in a remaining portion of the material stack not including the trench and at least one shallow trench contact in the third conductive material.
Dependencies are inferred from the claim text.