Wiring line layout in a semiconductor memory device

A semiconductor device, comprising:

• a plurality of first selection lines in a first region in a first selection line layer;
• a plurality of first opening regions in a second region in the first selection line layer, wherein
• the first region is different from the second region,
• each of the plurality of first selection lines has a first width,
• each of the plurality of first selection lines extends in a first direction,
• a first selection line of the plurality of first selection lines is adjacent to a second selection line of the plurality of first selection lines in a second direction, and
• the second direction intersects with the first direction;
• a first metal wiring line in a first layer above the first selection line layer;
• a first through wiring line, wherein
• the first through wiring line penetrates a first insulating layer on the first selection line layer,
• a first end of the first through wiring line is coupled to the first selection line,
• a second end of the first through wiring line is coupled to the first metal wiring line, and
• a thickness of the first through wiring line decreases from the second end coupled to the first metal wiring line to the first end coupled to the first selection line;
• a second through wiring line in a first opening region of the plurality of first opening regions;
• a third through wiring line in a second opening region of the plurality of first opening regions, wherein
• each of the second through wiring line and the third through wiring line penetrates the first selection line layer, and
• a first end of the second through wiring line is coupled to the first metal wiring line;
• a first storage element that comprises a first terminal and a second terminal,
• wherein the second terminal of the first storage element is coupled to the first selection line;
• and
• a first drive circuit coupled to a second end of the second through wiring line,
• wherein the first drive circuit is configured to drive the plurality of first selection lines.