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US 11,081,515 B2Granted
Semiconducting device, and appliance having the semiconducting device
AssigneeCanon Kabushiki Kaisha
InventorsTakehiko Soda, Kazutoshi Torashima, Yasushi Nakata
Life of this patent
Estimating the term…
Abstract
A first conductive pattern and a third conductive pattern are joined to each other in a junction plane, and a second conductive pattern and a fourth conductive pattern are joined to each other in the junction plane, and an insulation layer is arranged at least in one of spaces between the first conductive pattern and the second conductive pattern and between the third conductive pattern and the fourth conductive pattern.
Claims29
A semiconducting device comprising:
- a first chip having a plurality of pixels that are arranged over a plurality of rows and a plurality of columns, each pixel having a photoelectric conversion unit and an output node which outputs a signal level corresponding to an electric charge of the photoelectric conversion unit;
- a second chip in which a plurality of cells are arranged, wherein the first chip has a plurality of conductive patterns of the first chip, the plurality of conductive patterns of the first chip each containing copper as a main component,
- the second chip has a plurality of conductive patterns of the second chip, the plurality of conductive patterns of the second chip each containing copper as a main component,
- each of the plurality of the conductive patterns of the first chip and each of the plurality of the conductive patterns of the second chip are joined to each other on a junction plane, and
- in the first chip, the number of the conductive patterns corresponding to one wiring for transmitting a signal to be output from the output node of the one pixel of the first chip to at least one cell of the plurality of cells of the second chip is larger than the number of the conductive pattern corresponding to one wiring for transmitting a signal to be output from the second chip to the first chip.
2 more elements
A semiconductor device comprising:
- a first chip having a plurality of pixels that are arranged over a plurality of rows and a plurality of columns, each pixel having a photoelectric conversion unit and an output node which outputs a signal corresponding to an electric charge of the photoelectric conversion unit;
- and
- a second chip in which a plurality of cells are arranged, wherein
- the first chip has a plurality of conductive patterns of the first chip, the plurality of conductive patterns of the first chip each containing copper as a main component,
- the second chip has a plurality of conductive patterns of the second chip, the plurality of conductive patterns of the second chip each containing copper as a main component,
- each of the plurality of the conductive patterns of the first chip and each of the plurality of the conductive patterns of the second chip are joined to each other on a junction plane, and
- in the second chip, the number of the conductive patterns corresponding to one wiring for transmitting a signal to be output from the first chip to the second chip is larger than the number of the conductive pattern corresponding to one wiring for transmitting a signal to be output from the second chip to the first chip.
4 more elements
Dependencies are inferred from the claim text.