Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies

A NAND memory array, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels including control gate regions and second regions proximate the control gate regions;
• high-k dielectric material wrapping around ends of the control gate regions, and not being along said second regions, the high-k dielectric material being directly against conductive material of the control gate regions;
• charge-blocking material adjacent the high-k dielectric material, the charge-blocking material differing from the high-k dielectric material and comprising one or both of silicon oxynitride and silicon oxide;
• charge-storage material adjacent the charge-blocking material;
• the charge-storage material being configured as segments which are vertically-stacked one atop another, and which are vertically spaced from one another by gaps;
• gate-dielectric material adjacent the charge-storage material;
• and
• channel material extending vertically along the stack and being adjacent the gate-dielectric material.

A method of forming an integrated structure, comprising:

• forming a vertical stack of alternating first and second levels;
• the first levels comprising first material and the second levels comprising second material;
• forming an opening to extend through the stack;
• recessing the first levels relative to the second levels;
• the second levels having terminal ends extending beyond the recessed first levels;
• the terminal ends having surfaces of the second material;
• the recessed first levels having surfaces of the first material;
• the surfaces of the first and second materials forming an undulating sidewall surface of the opening;
• forming high-k dielectric material along the undulating sidewall surface;
• the high-k dielectric material wrapping around the terminal ends;
• the high-k dielectric material having first portions along the surfaces of the first material, and having second portions along the surfaces of the second material;
• forming charge-blocking material adjacent the high-k dielectric material;
• forming charge-storage material adjacent the charge-blocking material;
• forming gate-dielectric material adjacent the charge-storage material;
• forming channel material adjacent the gate-dielectric material;
• removing the second material to leave first voids;
• forming conductive levels within the first voids;
• the conductive levels having terminal regions adjacent the high-k dielectric material, and having nonterminal regions proximate the terminal regions;
• the high-k dielectric material wrapping around the terminal regions and not being along the nonterminal regions;
• removing the first material, the first portions of the high-k dielectric material, and regions of the charge-blocking material to leave second voids;
• and
• extending the second voids through the charge-storage material to divide the charge-storage material into vertically-spaced segments.