US 11,081,496 B2 · Three-dimensional memory devices and fabrication methods thereof

Abstract

Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.

Claims20

Dependent claims

A three-dimensional (3D) memory device, comprising:

a stack structure comprising a plurality of conductor layers insulated by a gate-to-gate dielectric structure over a substrate, wherein the gate-to-gate dielectric structure comprises at least one composite layer between adjacent conductor layers along a vertical direction perpendicular to a top surface of the substrate, wherein the at least one composite layer comprises at least a sub-layer of silicon oxynitride between a plurality of sub-layers of silicon oxide;
a semiconductor channel extending from a top surface of the stack structure to the substrate, wherein the semiconductor channel comprises a memory layer comprising a first memory portion surrounding a bottom of each conductor layer and a second memory portion connecting adjacent first memory portions, the first memory portion and the second memory portion being staggered along the vertical direction;
and
a source structure extending from the top surface of the stack structure to the substrate.

1 more element

A three-dimensional (3D) memory device, comprising:

a stack structure comprising a plurality of conductor layers insulated by a gate-to-gate dielectric structure over a substrate, wherein the gate-to-gate dielectric structure comprises at least one composite layer between adjacent conductor layers along a vertical direction perpendicular to a top surface of the substrate, wherein the at least one composite layer comprises at least a sub-layer of silicon oxynitride in contact with a pair of sub-layers of silicon oxide;
a semiconductor channel extending from a top surface of the stack structure to the substrate, wherein the semiconductor channel comprises a memory layer comprising a first memory portion surrounding a bottom of each conductor layer and a second memory portion connecting adjacent first memory portions, the first memory portion and the second memory portion being staggered along the vertical direction;
and
a source structure extending from the top surface of the stack structure to the substrate.

1 more element

Dependencies are inferred from the claim text.

Three-dimensional memory devices and fabrication methods thereof

Life of this patent

Three-dimensional memory devices and fabrication methods thereof

Life of this patent

Abstract

Claims20