Integrated circuit with vertically structured capacitive element, and its fabricating process

A process, comprising:

• fabricating a capacitive element on and in a well located within a semiconductor substrate, wherein said well is doped with a first conductivity type, wherein fabricating the capacitive element comprises:
• forming a trench extending vertically into said well from a first side of the well;
• forming an insulating cladding on sides and a bottom of said trench;
• forming a conductive material in a central section of said trench clad with the insulating cladding;
• forming a first insulating layer on the first side and a first conductive layer covering the first insulating layer;
• electrically connecting the conductive central section and the first conductive layer to form a first electrode of the capacitive element;
• forming a second insulating layer on the first conductive layer and a second conductive layer covering the second insulating layer;
• and
• electrically connecting the second conductive layer and the well to form a second electrode of the capacitive element.