Integrated circuit layout with asymmetric metal lines

A semiconductor device, comprising:

• a first group of semiconductor fins and a second group of semiconductor fins extending along a first direction and spaced apart by a fin-free region;
• a first gate structure and a second gate structure extending across the first group of semiconductor fins, the fin-free region, and the second group of semiconductor fins along a second direction different from the first direction;
• a first metal line and a second metal line extending within the fin-free region along the first direction;
• a first gate contact overlapping an intersection of the first metal line and the first gate structure from a top view;
• a second gate contact overlapping an intersection of the second metal line and the second gate structure from the top view;
• and
• a Vdd line and a Vss line extending on the same level as the first and second metal lines, wherein the Vdd line is adjacent the first group of semiconductor fins, the Vss line is adjacent the second group of semiconductor fins, and the Vdd line and the Vss line have different widths.

A method, comprising:

• generating, in a layout, a first group of fin layout patterns and a second group of fin layout patterns extending along a first direction, the first group of fin layout patterns and the second group of fin layout patterns being symmetric about a symmetric axis;
• generating, in the layout, a plurality of gate layout patterns extending along a second direction across the first group of fin layout patterns and the second group of fin layout patterns, the second direction being different from the first direction;
• generating, in the layout, a plurality of metal line layout patterns extending along the first direction across the plurality of gate layout patterns, the metal line layout patterns being asymmetric about the symmetric axis of the first group of fin layout patterns and the second group of fin layout patterns;
• and
• fabricating a semiconductor device based on the layout.