Integrated circuit structure and method for reducing polymer layer delamination

A method for forming an integrated circuit structure, comprising:

• providing a substrate with a metal pad;
• forming a first polymer layer with a first opening over the substrate to expose a portion of the metal pad;
• forming a second polymer layer with a second opening over the first polymer layer;
• forming a post-passivation interconnect (PPI) structure in electrical contact with the metal pad, wherein the PPI structure including a first portion extending into the second opening and a second portion extending along a top surface of the second polymer layer;
• depositing a third polymer layer over the PPI structure;
• removing a portion of the third polymer layer to form a third opening and expose at least a portion of the PPI structure;
• forming an underbump metallization (UBM) through the third opening, a portion of the UBM extending over a first portion of a surface of the third polymer layer facing away from the PPI structure, while leaving a second portion of the surface of the third polymer layer exposed, the UBM physically contacting the PPI structure;
• and
• exposing the third polymer layer to a plasma after the forming the UBM, the exposing of the third polymer layer to the plasma introducing hydrogen ions into the third polymer layer and forming a barrier layer from the second portion of the surface of the third polymer layer, the barrier layer having a hydrogen concentration greater than a hydrogen concentration of the third polymer layer, wherein a sidewall of the barrier layer is vertically aligned with a sidewall of the UBM.

A method for forming an integrated circuit structure, comprising:

• forming a first semiconductor die and a second semiconductor die separated from the first semiconductor die with an interval, wherein forming the first semiconductor die and the second semiconductor die each comprises:
• forming a first opening in a first passivation layer to expose a metal pad;
• forming a first polymer layer over the first passivation layer and the metal pad;
• and
• forming a post-passivation interconnect (PPI) pad extending through the first opening and in electrical contact with the metal pad, wherein the first polymer layer contacts portions of the metal pad after forming the PPI pad;
• filling the interval with an encapsulant;
• planarizing the encapsulant such that a top surface of the first polymer layer, a top surface of each of the PPI pads, the first semiconductor die, the second semiconductor die, and the encapsulant are level with one another;
• forming a second polymer layer over the first polymer layer, the PPI pads, and the encapsulant;
• patterning the second polymer layer to form a second opening exposing the PPI pad of each of the first semiconductor die and the second semiconductor die;
• forming a post-passivation interconnect (PPI) structure in the second opening and in electrical contact with the PPI pad of each of the first semiconductor die and the second semiconductor die, the PPI structure extending along a top surface of the second polymer layer;
• depositing a third polymer layer over the PPI structure of each of the first semiconductor die and the second semiconductor die;
• forming an underbump metallization (UBM) over each PPI structure, each UBM extending through the third polymer layer, and physically contacting the PPI structure of each of the first semiconductor die and the second semiconductor die;
• and
• forming a barrier layer by exposing a portion of the third polymer layer to a hydrogen plasma, the barrier layer having a hydrogen concentration higher than a hydrogen concentration of an unexposed portion of the third polymer layer, wherein a sidewall of the barrier layer is vertically aligned with a sidewall of the UBM of each of the first semiconductor die and the second semiconductor die.