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US 11,081,469 B2Granted
Three-dimensional integrated circuit test and improved thermal dissipation
AssigneeArm Limited
InventorsSaurabh Pijuskumar Sinha, Joel Thornton Irby, Supreet Jeloka
Life of this patent
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Abstract
A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.
Claims8
A three-dimensional (3D) integrated circuit (IC) comprising:
- a bottom tier comprising first circuitry and first backside TSVs coupled to a substrate;
- a top tier coupled to the first tier at a front side, the top tier comprising second circuitry and second backside TSVs;
- and
- a heat conductor on the second backside TSVs of the top tier.
1 more element
Dependencies are inferred from the claim text.