Back to results
US 11,081,451 B2Granted
Die stack with reduced warpage
AssigneeIntel Corporation
InventorsYong She, Bin Liu, Zhicheng Ding, Aiping Tan
Life of this patent
Estimating the term…
Abstract
A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.
Claims23
A microelectronic device comprising:
- a polymer layer including a first coefficient of thermal expansion;
- a semiconductor, wherein the polymer layer is located on a first side of the semiconductor;
- a matching layer directly coupled with the semiconductor, wherein:
- the matching layer is located on a second side of the semiconductor;
- and
- the matching layer including a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.
3 more elements
A microelectronic device comprising:
- a polymer layer;
- a semiconductor spaced from the polymer layer, wherein the polymer layer is located on a first side of the semiconductor;
- a signal distribution layer disposed between the polymer layer and the semiconductor, the signal distribution layer including a first coefficient of thermal expansion;
- a matching layer directly coupled with a second side of the semiconductor, the matching layer including a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.
1 more element
A microelectronic device package, comprising:
- a substrate including a plurality of conductive elements;
- a plurality of NAND modules oriented in a stacked configuration relative to the substrate, each NAND module electrically connected to one of the plurality of conductive elements, each NAND module comprising:
- a polymer layer including a first coefficient of thermal expansion;
- a semiconductor;
- a signal distribution layer disposed between the semiconductor and the polymer layer, the signal distribution layer including a second coefficient of thermal expansion;
- and
- a matching layer directly coupled with a second side of the semiconductor, the matching layer including a third coefficient of thermal expansion that is about the same as one or more of the first coefficient of thermal expansion and the second coefficient of thermal expansion;
- and
- an encapsulation layer enclosing the plurality of NAND modules.
6 more elements
A method of forming a microelectronic device, comprising:
- providing a wafer comprising a polymer layer including a first coefficient of thermal expansion, a distribution layer including a second coefficient of thermal expansion, and a semiconductor, wherein the polymer layer is located on a first side of the semiconductor;
- coating a second side of the semiconductor with a material having a third coefficient of thermal expansion that is about the same as one or more of the first coefficient of thermal expansion and the second coefficient of thermal expansion, wherein the material is directly coupled with the semiconductor;
- and
- curing the material.
1 more element
Dependencies are inferred from the claim text.