Interposer and semiconductor package including the same

An interposer comprising:

• a base substrate;
• an interconnection structure arranged on a top surface of the base substrate and comprising a metal interconnection pattern;
• an upper passivation layer covering a top surface of the interconnection structure and having compressive stress;
• a connection pad arranged on the top surface of the interconnection structure and electrically connected to the metal interconnection pattern of the interconnection structure, a bottom surface of the connection pad being coplanar with a bottom surface of the upper passivation layer;
• and
• a lower passivation layer covering a bottom surface of the base substrate and having compressive stress,
• wherein a thickness of the upper passivation layer is greater than or equal to a thickness of the connection pad,
• wherein each of the upper passivation layer and the lower passivation layer comprises a multilayer structure comprising a silicon oxide layer and a silicon nitride layer, and
• wherein the silicon oxide layer of the upper passivation layer is on the top surface of the interconnection structure, and the silicon nitride layer of the upper passivation layer is on the silicon oxide layer of the upper passivation layer.

A semiconductor package comprising:

• an interposer;
• and at least one semiconductor chip arranged on the interposer,
• wherein the interposer comprises:
• a base substrate;
• an interconnection structure arranged on a top surface of the base substrate and comprising a metal interconnection pattern;
• a connection pad arranged on the interconnection structure and electrically connected to the metal interconnection pattern of the interconnection structure;
• an upper passivation layer arranged on the interconnection structure, covering a portion of the connection pad, and having compressive stress;
• a lower passivation layer arranged on a bottom surface of the base substrate and having compressive stress;
• a lower conductive layer on the lower passivation layer;
• and
• a through electrode penetrating the base substrate and the lower passivation layer and electrically connecting the lower conductive layer to the metal interconnection pattern of the interconnection structure,
• wherein a thickness of the lower passivation layer is greater than a thickness of the upper passivation layer.