3D IC power grid
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNoor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
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Abstract
A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
Claims20
An apparatus comprising:
- a first integrated circuit (IC) die;
- a second IC die stacked on the first IC die;
- an interface disposed between the first IC die and the second IC die, wherein the interface comprises:
- a plurality of hybrid layer pins corresponding to the second IC die;
- a plurality of hybrid layer bumps corresponding to the first IC die;
- and
- a plurality of vertical top metal elements corresponding to the first IC die,
- wherein the plurality of hybrid layer pins connect to the plurality of hybrid layer bumps which connect to the plurality of vertical top metal elements;
- and
- a power distribution structure connected to the interface, the power distribution structure comprising:
- at least one Through-Silicon Via (TSV) connected to a power supply, and
- a ladder structure connected to the at least one TSV and the interface.
An apparatus comprising:
- a first integrated circuit (IC) die;
- a second IC die stacked on the first IC die in a face-to-face configuration;
- an interface disposed between the first IC die and the second IC die, wherein the interface comprises:
- a plurality of hybrid layer pins corresponding to the second IC die,
- a plurality of hybrid layer bumps corresponding to the first IC die, and
- a plurality of vertical top metal elements corresponding to the first IC die,
- wherein the plurality of hybrid layer pins connect to the plurality of hybrid layer bumps which connect to the plurality of vertical top metal elements;
- and
- a power distribution structure connected to the interface, wherein the power distribution structure passes through the first IC die, the power distribution structure comprising:
- at least one Through-Silicon Via (TSV) connected to a power supply, and
- a ladder structure connected to the least one TSV and the interface,
- wherein the ladder structure comprises a plurality of horizontal elements connected by a plurality of vertical elements.
A method comprising:
- providing a first integrated circuit (IC) die comprising a first functional element;
- stacking a second IC die comprising a second functional element on the first IC die;
- providing a first package bump on the first IC die, the first package bump being configured to connect to a first power supply
- providing a second package bump on the second IC die, the second package bump being configured to connect to a second power supply;
- and
- forming a power distribution structure in the first IC die, the power distribution structure comprising at least one Through-Silicon Via (TSV) connected to the first power supply and a ladder structure connected to the at least one TSV and the interface, wherein the ladder structure comprises a plurality of horizontal elements connected by a plurality of vertical elements.
Dependencies are inferred from the claim text.