Power semiconductor module arrangement

A power semiconductor module arrangement, comprising:

• a housing comprising sidewalls and a cover;
• a substrate arranged in the housing, the substrate comprising a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, the dielectric insulation layer being disposed between the first and the second metallization layers;
• at least one semiconductor body mounted on a first surface of the first metallization layer which faces away from the dielectric insulation layer;
• a connecting element arranged on and electrically connected to the first surface of the first metallization layer;
• a contact element inserted into and electrically connected to the connecting element, the contact element extending from the connecting element through the interior of the housing and through an opening in the cover of the housing to an outside of the housing in a direction perpendicular to the first surface;
• and
• a hard encapsulation arranged adjacent to the first metallization layer, the hard encapsulation at least partly filling an inside of the housing.