US 11,081,411 B2 · Semiconductor structure

Abstract

A semiconductor structure (100; 200) is provided. The semiconductor structure (100; 200) comprises a substrate (5); a plurality of test structures (101, 102, 201, 202) on the substrate, wherein the plurality of test structures comprise a first set of test structures (101, 102) and a second set of test structures (201, 202); a plurality of test electrodes (10, 20, 30) provided on the substrate, wherein the test electrodes comprise a first set of electrodes (10) operatively connected to the first set of test structures (101, 102), and a second set of electrodes (20) operatively connected to the second set of test structures (201, 202), wherein the first set of electrodes (10) are spaced apart from one another by a predetermined pitch and are configured to be operatively connectable to a probe card (8) having a plurality of probe pins (7) spaced apart from one another by the predetermined pitch to test the first set of test structures, and wherein the second set of electrodes (20) are spaced apart from one another by the predetermined pitch and are configured to be operatively connectable to the probe card (8) to test the second set of test structures; and wherein at least one electrode within the second set of electrodes (20) is disposed between adjacent electrodes within the first set of electrodes (10) along a length of the first set of electrodes (V).

Claims20

Dependent claims

A semiconductor structure comprising:

a substrate;
a plurality of test structures on the substrate, wherein the plurality of test structures comprise a first set of test structures and a second set of test structures;
a plurality of test electrodes provided on the substrate, wherein the test electrodes comprise a first set of electrodes operatively connected to the first set of test structures, and a second set of electrodes operatively connected to the second set of test structures, wherein the first set of electrodes are spaced apart from one another by a first distance and are configured to be operatively connectable to a probe card having a plurality of probe pins spaced apart from one another by the first distance to test the first set of test structures, and wherein the second set of electrodes are spaced apart from one another by the first distance and are configured to be operatively connectable to the probe card to test the second set of test structures;
and
wherein at least one electrode within the second set of electrodes is disposed between adjacent electrodes within the first set of electrodes along a length of the first set of electrodes.

2 more elements

A method of testing a semiconductor structure using a probe card, wherein the probe card comprises a plurality of probe pins spaced apart from one another by a first distance, the method comprising:

providing a semiconductor structure, the semiconductor structure comprising:
a substrate;
a plurality of test structures on the substrate, wherein the plurality of test structures comprise a first set of test structures and a second set of test structures;
and
a plurality of test electrodes on the substrate, wherein the test electrodes comprise a first set of electrodes operatively connected to the first set of test structures, and a second set of electrodes operatively connected to the second set of test structures, wherein the first set of electrodes are spaced apart from one another by the first distance, and the second set of electrodes are spaced apart from one another by the first distance, and wherein at least one electrode within the second set of electrodes is disposed between adjacent electrodes within the first set of electrodes along a length of the first set of electrodes;
operatively connecting the probe pins to the first set of electrodes to test the first set of test structures;
and
operatively connecting the probe pins to the second set of electrodes to test the second set of test structures.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor structure

Life of this patent

Semiconductor structure

Life of this patent

Abstract

Claims20