Replacement gate process for semiconductor devices

A method comprising:

• forming a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer and a first hard mask layer over the gate electrode layer, wherein the second gate stack extends to a different height over the substrate than the first gate stack;
• forming a dielectric layer over the first and second gate stacks;
• performing a first planarization process to remove a first portion of the dielectric layer over the first and second gate stacks, wherein a second portion of the of the dielectric layer is disposed directly over the first gate while no portions of the dielectric layer are disposed directly over the second gate stack after the performing of the first planarization process, wherein the first planarization process includes applying a slurry to remove the first portion of the dielectric layer from over the first and second gate stacks;
• performing an etching process to expose the first hard mask layer in the first and second gate stacks, wherein the etching process includes applying a first etchant to expose the first hard mask layer in the first and second gate stacks, the first etchant that having a different material composition than the slurry;
• and
• performing a second planarization process to remove the first hard mask layer in at least the second gate stack.

A method comprising:

• forming a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer, wherein the second gate stack extends to a different height over the substrate than the first gate stack, wherein the first and second gate stacks each further includes a first hard mask layer disposed over the gate electrode layer and a second hard mask layer disposed over the first hard mask layer;
• forming an etch stop layer (ESL) on the first and second gate stacks;
• forming an inter-layer dielectric (ILD) layer on the ESL;
• removing a first portion of the ILD layer to expose the ESL over the first gate stack while a second portion of the ILD layer covers the ESL disposed over the second gate stack;
• removing the second portion of the ILD layer and the ESL layer over the first and second gate stacks to expose a portion of the first and second gate stacks, wherein the exposed portion of the first and second gate stacks includes exposing the second hard mask layer in the first and second gate stacks;
• and
• removing the exposed portion of the first and second gate stacks to expose the gate electrode layer in the first and second gate stacks.